Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.20	94.16	96.15	97.08		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.20	94.16	96.15	97.08		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T59,T128

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T11,T29,T52

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T73,T142
1	Covered	T73,T142

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7
1	1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T6,T8

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T6,T8

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T4
ReadWaitSt	252	Covered	T2,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T3,T4
IdleSt->ReadSt	236	Covered	T2,T3,T4
InitSt->ErrorSt	315	Covered	T2,T117,T183
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T118,T144,T171
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T6,T7,T39
ReadSt->ReadWaitSt	252	Covered	T2,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T195,T200,T201
ReadWaitSt->IdleSt	270	Covered	T2,T3,T4
ResetSt->ErrorSt	315	Covered	T71,T72,T73
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T6,T7,T39
CheckFailError	317	Covered	T73,T142
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Covered	T4,T11,T29
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T114,T15,T28
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T6,T7,T39
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T73,T142
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T4,T29,T59
MacroEccCorrError->NoError	235	Covered	T11,T29,T52
NoError->AccessError	256	Covered	T6,T7,T39
NoError->CheckFailError	317	Covered	T73,T142
NoError->FsmStateError	289	Covered	T1,T2,T3
NoError->MacroEccCorrError	221	Covered	T4,T11,T29

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T6,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T4,T59,T128
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T172,T202,T203
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T50,T109,T51
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T6,T7,T39
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T11,T29,T52
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T195,T200,T201
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T23,T24
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T7,T106
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T7,T106
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T73,T142
1	0	Covered	T73,T142
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	422770771	421898307	0	0
DigestKnown_A	422770771	421898307	0	0
DigestOffsetMustBeRepresentable_A	1145	1145	0	0
EccErrorState_A	422770771	7054	0	0
ErrorKnown_A	422770771	421898307	0	0
FsmStateKnown_A	422770771	421898307	0	0
InitDoneKnown_A	422770771	421898307	0	0
InitReadLocksPartition_A	422770771	77693925	0	0
InitWriteLocksPartition_A	422770771	77693925	0	0
OffsetMustBeBlockAligned_A	1145	1145	0	0
OtpAddrKnown_A	422770771	421898307	0	0
OtpCmdKnown_A	422770771	421898307	0	0
OtpErrorState_A	422770771	41	0	0
OtpReqKnown_A	422770771	421898307	0	0
OtpSizeKnown_A	422770771	421898307	0	0
OtpWdataKnown_A	422770771	421898307	0	0
ReadLockPropagation_A	422770771	176030214	0	0
SizeMustBeBlockAligned_A	1145	1145	0	0
TlulGntKnown_A	422770771	421898307	0	0
TlulRdataKnown_A	422770771	421898307	0	0
TlulReadOnReadLock_A	422770771	7745	0	0
TlulRerrorKnown_A	422770771	421898307	0	0
TlulRvalidKnown_A	422770771	421898307	0	0
WriteLockPropagation_A	422770771	2604610	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	422770771	30704430	0	0
u_state_regs_A	422770771	421898307	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	421898307	0	0
T1	12576	12290	0	0
T2	13420	13166	0	0
T3	15031	14826	0	0
T4	10627	10446	0	0
T5	13105	12864	0	0
T6	102238	101289	0	0
T7	256852	256842	0	0
T11	13053	12746	0	0
T12	11466	11243	0	0
T13	16232	16171	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	421898307	0	0
T1	12576	12290	0	0
T2	13420	13166	0	0
T3	15031	14826	0	0
T4	10627	10446	0	0
T5	13105	12864	0	0
T6	102238	101289	0	0
T7	256852	256842	0	0
T11	13053	12746	0	0
T12	11466	11243	0	0
T13	16232	16171	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1145	1145	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	7054	0	0
T73	13194	3223	0	0
T130	69688	0	0	0
T142	0	3831	0	0
T151	148756	0	0	0
T152	175774	0	0	0
T153	594048	0	0	0
T154	7996	0	0	0
T155	10273	0	0	0
T156	12486	0	0	0
T157	26104	0	0	0
T158	15922	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	421898307	0	0
T1	12576	12290	0	0
T2	13420	13166	0	0
T3	15031	14826	0	0
T4	10627	10446	0	0
T5	13105	12864	0	0
T6	102238	101289	0	0
T7	256852	256842	0	0
T11	13053	12746	0	0
T12	11466	11243	0	0
T13	16232	16171	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	421898307	0	0
T1	12576	12290	0	0
T2	13420	13166	0	0
T3	15031	14826	0	0
T4	10627	10446	0	0
T5	13105	12864	0	0
T6	102238	101289	0	0
T7	256852	256842	0	0
T11	13053	12746	0	0
T12	11466	11243	0	0
T13	16232	16171	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	421898307	0	0
T1	12576	12290	0	0
T2	13420	13166	0	0
T3	15031	14826	0	0
T4	10627	10446	0	0
T5	13105	12864	0	0
T6	102238	101289	0	0
T7	256852	256842	0	0
T11	13053	12746	0	0
T12	11466	11243	0	0
T13	16232	16171	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	77693925	0	0
T1	12576	3443	0	0
T2	13420	5169	0	0
T3	15031	3384	0	0
T4	10627	5481	0	0
T5	13105	4374	0	0
T6	102238	1339	0	0
T7	256852	955464	0	0
T11	13053	399	0	0
T12	11466	3792	0	0
T13	16232	269	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	77693925	0	0
T1	12576	3443	0	0
T2	13420	5169	0	0
T3	15031	3384	0	0
T4	10627	5481	0	0
T5	13105	4374	0	0
T6	102238	1339	0	0
T7	256852	955464	0	0
T11	13053	399	0	0
T12	11466	3792	0	0
T13	16232	269	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1145	1145	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	421898307	0	0
T1	12576	12290	0	0
T2	13420	13166	0	0
T3	15031	14826	0	0
T4	10627	10446	0	0
T5	13105	12864	0	0
T6	102238	101289	0	0
T7	256852	256842	0	0
T11	13053	12746	0	0
T12	11466	11243	0	0
T13	16232	16171	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	421898307	0	0
T1	12576	12290	0	0
T2	13420	13166	0	0
T3	15031	14826	0	0
T4	10627	10446	0	0
T5	13105	12864	0	0
T6	102238	101289	0	0
T7	256852	256842	0	0
T11	13053	12746	0	0
T12	11466	11243	0	0
T13	16232	16171	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	41	0	0
T18	670211	0	0	0
T77	25451	0	0	0
T129	9072	0	0	0
T172	13435	1	0	0
T186	309773	0	0	0
T195	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0
T204	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T207	0	1	0	0
T208	0	1	0	0
T209	0	1	0	0
T210	173051	0	0	0
T211	32154	0	0	0
T212	13688	0	0	0
T213	27920	0	0	0
T214	380270	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	421898307	0	0
T1	12576	12290	0	0
T2	13420	13166	0	0
T3	15031	14826	0	0
T4	10627	10446	0	0
T5	13105	12864	0	0
T6	102238	101289	0	0
T7	256852	256842	0	0
T11	13053	12746	0	0
T12	11466	11243	0	0
T13	16232	16171	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	421898307	0	0
T1	12576	12290	0	0
T2	13420	13166	0	0
T3	15031	14826	0	0
T4	10627	10446	0	0
T5	13105	12864	0	0
T6	102238	101289	0	0
T7	256852	256842	0	0
T11	13053	12746	0	0
T12	11466	11243	0	0
T13	16232	16171	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	421898307	0	0
T1	12576	12290	0	0
T2	13420	13166	0	0
T3	15031	14826	0	0
T4	10627	10446	0	0
T5	13105	12864	0	0
T6	102238	101289	0	0
T7	256852	256842	0	0
T11	13053	12746	0	0
T12	11466	11243	0	0
T13	16232	16171	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	176030214	0	0
T6	102238	45884	0	0
T7	256852	197309	0	0
T8	41866	0	0	0
T9	424980	0	0	0
T11	13053	2092	0	0
T12	11466	0	0	0
T13	16232	0	0	0
T14	0	210948	0	0
T16	0	1081	0	0
T29	95125	4021	0	0
T30	0	48417	0	0
T39	0	18373	0	0
T50	0	313741	0	0
T105	7264	0	0	0
T106	16159	0	0	0
T114	0	10522	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1145	1145	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	421898307	0	0
T1	12576	12290	0	0
T2	13420	13166	0	0
T3	15031	14826	0	0
T4	10627	10446	0	0
T5	13105	12864	0	0
T6	102238	101289	0	0
T7	256852	256842	0	0
T11	13053	12746	0	0
T12	11466	11243	0	0
T13	16232	16171	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	421898307	0	0
T1	12576	12290	0	0
T2	13420	13166	0	0
T3	15031	14826	0	0
T4	10627	10446	0	0
T5	13105	12864	0	0
T6	102238	101289	0	0
T7	256852	256842	0	0
T11	13053	12746	0	0
T12	11466	11243	0	0
T13	16232	16171	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	7745	0	0
T1	12576	2	0	0
T2	13420	0	0	0
T3	15031	0	0	0
T4	10627	0	0	0
T5	13105	0	0	0
T6	102238	10	0	0
T7	256852	6	0	0
T9	0	15	0	0
T10	0	18	0	0
T11	13053	0	0	0
T12	11466	0	0	0
T13	16232	0	0	0
T30	0	7	0	0
T39	0	1	0	0
T106	0	9	0	0
T114	0	8	0	0
T146	0	11	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	421898307	0	0
T1	12576	12290	0	0
T2	13420	13166	0	0
T3	15031	14826	0	0
T4	10627	10446	0	0
T5	13105	12864	0	0
T6	102238	101289	0	0
T7	256852	256842	0	0
T11	13053	12746	0	0
T12	11466	11243	0	0
T13	16232	16171	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	421898307	0	0
T1	12576	12290	0	0
T2	13420	13166	0	0
T3	15031	14826	0	0
T4	10627	10446	0	0
T5	13105	12864	0	0
T6	102238	101289	0	0
T7	256852	256842	0	0
T11	13053	12746	0	0
T12	11466	11243	0	0
T13	16232	16171	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	2604610	0	0
T6	102238	37093	0	0
T7	256852	0	0	0
T8	41866	0	0	0
T9	424980	0	0	0
T12	11466	0	0	0
T13	16232	0	0	0
T29	95125	1980	0	0
T30	0	21336	0	0
T39	34375	0	0	0
T50	0	101083	0	0
T51	0	2107	0	0
T52	0	11993	0	0
T98	0	4782	0	0
T99	0	49077	0	0
T100	0	9252	0	0
T101	0	10873	0	0
T105	7264	0	0	0
T106	16159	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	30704430	0	0
T6	102238	87139	0	0
T7	256852	0	0	0
T8	41866	12684	0	0
T9	424980	0	0	0
T11	13053	4088	0	0
T12	11466	0	0	0
T13	16232	0	0	0
T29	95125	14748	0	0
T30	0	113078	0	0
T39	0	18095	0	0
T50	0	746123	0	0
T105	7264	0	0	0
T106	16159	2679	0	0
T114	0	2533	0	0
T146	0	4192	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	421898307	0	0
T1	12576	12290	0	0
T2	13420	13166	0	0
T3	15031	14826	0	0
T4	10627	10446	0	0
T5	13105	12864	0	0
T6	102238	101289	0	0
T7	256852	256842	0	0
T11	13053	12746	0	0
T12	11466	11243	0	0
T13	16232	16171	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T57,T128

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T29,T15,T52

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T143,T145
1	Covered	T143,T145

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7
1	1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T29,T146

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T29,T146

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T2,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T3,T4
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T2,T117,T118
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T172,T212,T202
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T6,T7
ReadSt->ReadWaitSt	252	Covered	T2,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T149,T215,T216
ReadWaitSt->IdleSt	270	Covered	T2,T3,T4
ResetSt->ErrorSt	315	Covered	T71,T72,T73
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T6,T7
CheckFailError	317	Covered	T143,T145
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Covered	T5,T29,T15
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T1,T7,T10
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T6,T39,T30
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T143,T145
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T5,T29,T57
MacroEccCorrError->NoError	235	Covered	T29,T15,T52
NoError->AccessError	256	Covered	T1,T6,T7
NoError->CheckFailError	317	Covered	T143,T145
NoError->FsmStateError	289	Covered	T2,T3,T4
NoError->MacroEccCorrError	221	Covered	T5,T29,T15

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T29,T146
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T5,T57,T128
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T212,T217,T218
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T14,T50,T98
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T6,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T29,T15,T52
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T149,T215,T216
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T23,T24
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T7,T106
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T7,T106
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T143,T145
1	0	Covered	T143,T145
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	422770771	421898307	0	0
DigestKnown_A	422770771	421898307	0	0
DigestOffsetMustBeRepresentable_A	1145	1145	0	0
EccErrorState_A	422770771	7384	0	0
ErrorKnown_A	422770771	421898307	0	0
FsmStateKnown_A	422770771	421898307	0	0
InitDoneKnown_A	422770771	421898307	0	0
InitReadLocksPartition_A	422770771	77875342	0	0
InitWriteLocksPartition_A	422770771	77875342	0	0
OffsetMustBeBlockAligned_A	1145	1145	0	0
OtpAddrKnown_A	422770771	421898307	0	0
OtpCmdKnown_A	422770771	421898307	0	0
OtpErrorState_A	422770771	39	0	0
OtpReqKnown_A	422770771	421898307	0	0
OtpSizeKnown_A	422770771	421898307	0	0
OtpWdataKnown_A	422770771	421898307	0	0
ReadLockPropagation_A	422770771	172232109	0	0
SizeMustBeBlockAligned_A	1145	1145	0	0
TlulGntKnown_A	422770771	421898307	0	0
TlulRdataKnown_A	422770771	421898307	0	0
TlulReadOnReadLock_A	422770771	7393	0	0
TlulRerrorKnown_A	422770771	421898307	0	0
TlulRvalidKnown_A	422770771	421898307	0	0
WriteLockPropagation_A	422770771	919672	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	422770771	12111528	0	0
u_state_regs_A	422770771	421898307	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	421898307	0	0
T1	12576	12290	0	0
T2	13420	13166	0	0
T3	15031	14826	0	0
T4	10627	10446	0	0
T5	13105	12864	0	0
T6	102238	101289	0	0
T7	256852	256842	0	0
T11	13053	12746	0	0
T12	11466	11243	0	0
T13	16232	16171	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	421898307	0	0
T1	12576	12290	0	0
T2	13420	13166	0	0
T3	15031	14826	0	0
T4	10627	10446	0	0
T5	13105	12864	0	0
T6	102238	101289	0	0
T7	256852	256842	0	0
T11	13053	12746	0	0
T12	11466	11243	0	0
T13	16232	16171	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1145	1145	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	7384	0	0
T63	72716	0	0	0
T143	14424	4014	0	0
T145	0	3370	0	0
T159	10514	0	0	0
T160	14945	0	0	0
T161	86567	0	0	0
T162	44732	0	0	0
T163	154302	0	0	0
T164	89605	0	0	0
T165	15865	0	0	0
T166	40337	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	421898307	0	0
T1	12576	12290	0	0
T2	13420	13166	0	0
T3	15031	14826	0	0
T4	10627	10446	0	0
T5	13105	12864	0	0
T6	102238	101289	0	0
T7	256852	256842	0	0
T11	13053	12746	0	0
T12	11466	11243	0	0
T13	16232	16171	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	421898307	0	0
T1	12576	12290	0	0
T2	13420	13166	0	0
T3	15031	14826	0	0
T4	10627	10446	0	0
T5	13105	12864	0	0
T6	102238	101289	0	0
T7	256852	256842	0	0
T11	13053	12746	0	0
T12	11466	11243	0	0
T13	16232	16171	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	421898307	0	0
T1	12576	12290	0	0
T2	13420	13166	0	0
T3	15031	14826	0	0
T4	10627	10446	0	0
T5	13105	12864	0	0
T6	102238	101289	0	0
T7	256852	256842	0	0
T11	13053	12746	0	0
T12	11466	11243	0	0
T13	16232	16171	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	77875342	0	0
T1	12576	3494	0	0
T2	13420	5203	0	0
T3	15031	3418	0	0
T4	10627	5515	0	0
T5	13105	4425	0	0
T6	102238	1577	0	0
T7	256852	955566	0	0
T11	13053	467	0	0
T12	11466	3826	0	0
T13	16232	286	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	77875342	0	0
T1	12576	3494	0	0
T2	13420	5203	0	0
T3	15031	3418	0	0
T4	10627	5515	0	0
T5	13105	4425	0	0
T6	102238	1577	0	0
T7	256852	955566	0	0
T11	13053	467	0	0
T12	11466	3826	0	0
T13	16232	286	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1145	1145	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	421898307	0	0
T1	12576	12290	0	0
T2	13420	13166	0	0
T3	15031	14826	0	0
T4	10627	10446	0	0
T5	13105	12864	0	0
T6	102238	101289	0	0
T7	256852	256842	0	0
T11	13053	12746	0	0
T12	11466	11243	0	0
T13	16232	16171	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	421898307	0	0
T1	12576	12290	0	0
T2	13420	13166	0	0
T3	15031	14826	0	0
T4	10627	10446	0	0
T5	13105	12864	0	0
T6	102238	101289	0	0
T7	256852	256842	0	0
T11	13053	12746	0	0
T12	11466	11243	0	0
T13	16232	16171	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	39	0	0
T18	670211	0	0	0
T47	13815	0	0	0
T77	25451	0	0	0
T120	10481	0	0	0
T149	0	1	0	0
T202	12234	0	0	0
T212	13688	1	0	0
T213	27920	0	0	0
T214	380270	0	0	0
T217	0	1	0	0
T218	0	1	0	0
T219	0	1	0	0
T220	0	1	0	0
T221	0	1	0	0
T222	0	1	0	0
T223	0	1	0	0
T224	0	1	0	0
T225	65155	0	0	0
T226	115979	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	421898307	0	0
T1	12576	12290	0	0
T2	13420	13166	0	0
T3	15031	14826	0	0
T4	10627	10446	0	0
T5	13105	12864	0	0
T6	102238	101289	0	0
T7	256852	256842	0	0
T11	13053	12746	0	0
T12	11466	11243	0	0
T13	16232	16171	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	421898307	0	0
T1	12576	12290	0	0
T2	13420	13166	0	0
T3	15031	14826	0	0
T4	10627	10446	0	0
T5	13105	12864	0	0
T6	102238	101289	0	0
T7	256852	256842	0	0
T11	13053	12746	0	0
T12	11466	11243	0	0
T13	16232	16171	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	421898307	0	0
T1	12576	12290	0	0
T2	13420	13166	0	0
T3	15031	14826	0	0
T4	10627	10446	0	0
T5	13105	12864	0	0
T6	102238	101289	0	0
T7	256852	256842	0	0
T11	13053	12746	0	0
T12	11466	11243	0	0
T13	16232	16171	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	172232109	0	0
T1	12576	5856	0	0
T2	13420	0	0	0
T3	15031	0	0	0
T4	10627	0	0	0
T5	13105	0	0	0
T6	102238	36824	0	0
T7	256852	191415	0	0
T10	0	23995	0	0
T11	13053	1993	0	0
T12	11466	0	0	0
T13	16232	0	0	0
T16	0	1074	0	0
T29	0	893	0	0
T30	0	53496	0	0
T39	0	16532	0	0
T146	0	61793	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1145	1145	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	421898307	0	0
T1	12576	12290	0	0
T2	13420	13166	0	0
T3	15031	14826	0	0
T4	10627	10446	0	0
T5	13105	12864	0	0
T6	102238	101289	0	0
T7	256852	256842	0	0
T11	13053	12746	0	0
T12	11466	11243	0	0
T13	16232	16171	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	421898307	0	0
T1	12576	12290	0	0
T2	13420	13166	0	0
T3	15031	14826	0	0
T4	10627	10446	0	0
T5	13105	12864	0	0
T6	102238	101289	0	0
T7	256852	256842	0	0
T11	13053	12746	0	0
T12	11466	11243	0	0
T13	16232	16171	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	7393	0	0
T1	12576	3	0	0
T2	13420	0	0	0
T3	15031	0	0	0
T4	10627	0	0	0
T5	13105	0	0	0
T6	102238	7	0	0
T7	256852	2	0	0
T9	0	26	0	0
T10	0	24	0	0
T11	13053	0	0	0
T12	11466	0	0	0
T13	16232	0	0	0
T30	0	8	0	0
T39	0	2	0	0
T106	0	13	0	0
T114	0	4	0	0
T146	0	16	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	421898307	0	0
T1	12576	12290	0	0
T2	13420	13166	0	0
T3	15031	14826	0	0
T4	10627	10446	0	0
T5	13105	12864	0	0
T6	102238	101289	0	0
T7	256852	256842	0	0
T11	13053	12746	0	0
T12	11466	11243	0	0
T13	16232	16171	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	421898307	0	0
T1	12576	12290	0	0
T2	13420	13166	0	0
T3	15031	14826	0	0
T4	10627	10446	0	0
T5	13105	12864	0	0
T6	102238	101289	0	0
T7	256852	256842	0	0
T11	13053	12746	0	0
T12	11466	11243	0	0
T13	16232	16171	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	919672	0	0
T22	107575	0	0	0
T28	289670	0	0	0
T34	16736	0	0	0
T38	290823	0	0	0
T45	11305	0	0	0
T99	385600	87166	0	0
T100	139384	16569	0	0
T102	0	28995	0	0
T103	0	8947	0	0
T104	0	10964	0	0
T107	0	1208	0	0
T118	10912	0	0	0
T131	0	6972	0	0
T186	0	73333	0	0
T187	0	1887	0	0
T188	0	20082	0	0
T189	39775	0	0	0
T190	20555	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	12111528	0	0
T6	102238	0	0	0
T7	256852	0	0	0
T8	41866	0	0	0
T9	424980	0	0	0
T11	13053	4054	0	0
T12	11466	0	0	0
T13	16232	0	0	0
T29	95125	18278	0	0
T50	0	172126	0	0
T97	0	37291	0	0
T99	0	121391	0	0
T100	0	122734	0	0
T102	0	278881	0	0
T103	0	132161	0	0
T105	7264	0	0	0
T106	16159	0	0	0
T146	0	4158	0	0
T183	0	2411	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422770771	421898307	0	0
T1	12576	12290	0	0
T2	13420	13166	0	0
T3	15031	14826	0	0
T4	10627	10446	0	0
T5	13105	12864	0	0
T6	102238	101289	0	0
T7	256852	256842	0	0
T11	13053	12746	0	0
T12	11466	11243	0	0
T13	16232	16171	0	0