Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7469658	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7280743

1

T1

16535

T2

250

T3

319

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8601211	1			T1	14906		T2	988		T3	718
values[0x0]	2346598	1			T1	5998		T2	141		T3	46
values[0x1]	3802592	1			T1	10293		T2	143		T3	42

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4850744	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9899657

1

T1

22609

T2

526

T3

435

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	61578	1			T1	154		T3	3		T5	3
valid_sources[0x01]	54298	1			T1	111		T3	4		T5	3
valid_sources[0x02]	50109	1			T1	120		T3	4		T5	8
valid_sources[0x03]	52395	1			T1	139		T3	2		T5	4
valid_sources[0x04]	62404	1			T1	100		T3	6		T5	7
valid_sources[0x05]	55867	1			T1	112		T3	2		T5	5
valid_sources[0x06]	51895	1			T1	115		T3	3		T5	13
valid_sources[0x07]	65587	1			T1	124		T3	7		T5	12
valid_sources[0x08]	197659	1			T1	107		T3	5		T5	4
valid_sources[0x09]	51271	1			T1	127		T3	11		T5	7
valid_sources[0x0a]	69570	1			T1	124		T3	2		T5	12
valid_sources[0x0b]	52659	1			T1	132		T3	12		T5	6
valid_sources[0x0c]	50767	1			T1	112		T3	1		T5	7
valid_sources[0x0d]	65320	1			T1	105		T3	2		T5	3
valid_sources[0x0e]	52221	1			T1	117		T3	4		T5	6
valid_sources[0x0f]	52261	1			T1	99		T5	12		T4	10
valid_sources[0x10]	107999	1			T1	122		T3	3		T5	6
valid_sources[0x11]	52684	1			T1	115		T3	4		T5	14
valid_sources[0x12]	50893	1			T1	118		T3	6		T5	2
valid_sources[0x13]	72287	1			T1	136		T3	2		T5	6
valid_sources[0x14]	55500	1			T1	122		T3	2		T5	10
valid_sources[0x15]	64728	1			T1	135		T3	3		T5	8
valid_sources[0x16]	52612	1			T1	116		T3	5		T5	1
valid_sources[0x17]	51122	1			T1	109		T3	7		T5	2
valid_sources[0x18]	51356	1			T1	112		T3	1		T5	10
valid_sources[0x19]	54939	1			T1	152		T3	6		T5	6
valid_sources[0x1a]	55804	1			T1	115		T3	7		T5	14
valid_sources[0x1b]	50984	1			T1	136		T5	5		T4	6
valid_sources[0x1c]	51199	1			T1	138		T3	4		T5	8
valid_sources[0x1d]	65431	1			T1	123		T3	4		T5	2
valid_sources[0x1e]	55564	1			T1	114		T3	1		T5	2
valid_sources[0x1f]	51581	1			T1	120		T5	14		T4	22
valid_sources[0x20]	54819	1			T1	136		T5	8		T4	8
valid_sources[0x21]	68452	1			T1	134		T3	1		T5	12
valid_sources[0x22]	51597	1			T1	114		T3	1		T5	6
valid_sources[0x23]	60023	1			T1	132		T3	2		T5	6
valid_sources[0x24]	56581	1			T1	120		T3	2		T5	8
valid_sources[0x25]	52746	1			T1	100		T3	2		T5	5
valid_sources[0x26]	52140	1			T1	116		T3	2		T5	10
valid_sources[0x27]	51113	1			T1	120		T3	4		T5	8
valid_sources[0x28]	53008	1			T1	120		T3	2		T5	11
valid_sources[0x29]	57746	1			T1	132		T3	6		T5	9
valid_sources[0x2a]	55707	1			T1	119		T3	2		T5	7
valid_sources[0x2b]	51008	1			T1	135		T3	5		T5	6
valid_sources[0x2c]	51814	1			T1	107		T3	4		T5	8
valid_sources[0x2d]	53225	1			T1	119		T3	1		T5	13
valid_sources[0x2e]	68286	1			T1	109		T5	14		T4	10
valid_sources[0x2f]	55057	1			T1	131		T3	4		T5	9
valid_sources[0x30]	58326	1			T1	109		T3	2		T5	6
valid_sources[0x31]	52123	1			T1	122		T3	9		T5	6
valid_sources[0x32]	51911	1			T1	121		T3	3		T5	5
valid_sources[0x33]	50838	1			T1	114		T3	3		T5	4
valid_sources[0x34]	58751	1			T1	127		T3	4		T5	2
valid_sources[0x35]	52575	1			T1	121		T3	1		T5	1
valid_sources[0x36]	53259	1			T1	110		T3	3		T5	8
valid_sources[0x37]	49628	1			T1	123		T3	5		T5	3
valid_sources[0x38]	48723	1			T1	143		T5	8		T4	8
valid_sources[0x39]	52583	1			T1	130		T3	3		T5	6
valid_sources[0x3a]	52375	1			T1	109		T3	4		T5	3
valid_sources[0x3b]	53608	1			T1	119		T3	5		T5	10
valid_sources[0x3c]	53181	1			T1	141		T5	8		T4	8
valid_sources[0x3d]	52160	1			T1	112		T3	3		T5	4
valid_sources[0x3e]	50820	1			T1	131		T3	2		T5	2
valid_sources[0x3f]	52736	1			T1	120		T3	13		T5	1
valid_sources[0x40]	53905	1			T1	114		T5	12		T4	7
valid_sources[0x41]	49714	1			T1	119		T3	1		T5	9
valid_sources[0x42]	54713	1			T1	117		T3	5		T5	12
valid_sources[0x43]	60331	1			T1	140		T3	1		T5	8
valid_sources[0x44]	54443	1			T1	110		T3	1		T5	6
valid_sources[0x45]	51102	1			T1	117		T3	6		T5	7
valid_sources[0x46]	52181	1			T1	109		T3	1		T5	5
valid_sources[0x47]	54680	1			T1	137		T3	12		T5	5
valid_sources[0x48]	50065	1			T1	116		T3	2		T5	8
valid_sources[0x49]	56054	1			T1	128		T3	1		T5	2
valid_sources[0x4a]	71228	1			T1	109		T3	4		T5	4
valid_sources[0x4b]	63493	1			T1	102		T3	3		T5	6
valid_sources[0x4c]	51204	1			T1	128		T3	4		T5	3
valid_sources[0x4d]	52518	1			T1	123		T5	4		T4	11
valid_sources[0x4e]	53298	1			T1	111		T3	3		T5	11
valid_sources[0x4f]	53435	1			T1	128		T3	2		T5	12
valid_sources[0x50]	53759	1			T1	120		T3	4		T5	5
valid_sources[0x51]	51183	1			T1	102		T3	3		T5	4
valid_sources[0x52]	51342	1			T1	114		T3	1		T5	6
valid_sources[0x53]	56684	1			T1	122		T3	13		T5	16
valid_sources[0x54]	56048	1			T1	117		T5	12		T4	7
valid_sources[0x55]	53580	1			T1	118		T3	2		T5	5
valid_sources[0x56]	54223	1			T1	115		T3	9		T5	7
valid_sources[0x57]	58827	1			T1	127		T3	5		T5	13
valid_sources[0x58]	55328	1			T1	128		T3	3		T5	7
valid_sources[0x59]	56711	1			T1	132		T3	6		T5	4
valid_sources[0x5a]	56997	1			T1	113		T5	7		T4	5
valid_sources[0x5b]	52417	1			T1	128		T3	2		T5	2
valid_sources[0x5c]	50922	1			T1	105		T3	7		T5	11
valid_sources[0x5d]	57813	1			T1	111		T3	7		T5	6
valid_sources[0x5e]	65013	1			T1	121		T3	6		T5	9
valid_sources[0x5f]	50098	1			T1	129		T3	6		T5	2
valid_sources[0x60]	51678	1			T1	108		T3	1		T5	5
valid_sources[0x61]	50300	1			T1	128		T3	7		T5	4
valid_sources[0x62]	52863	1			T1	138		T3	4		T5	5
valid_sources[0x63]	56306	1			T1	102		T5	5		T4	11
valid_sources[0x64]	50692	1			T1	99		T3	2		T5	13
valid_sources[0x65]	53652	1			T1	120		T3	4		T5	6
valid_sources[0x66]	50210	1			T1	110		T3	2		T5	7
valid_sources[0x67]	49992	1			T1	120		T3	2		T5	7
valid_sources[0x68]	51238	1			T1	120		T3	2		T5	2
valid_sources[0x69]	55856	1			T1	141		T3	2		T5	8
valid_sources[0x6a]	52736	1			T1	123		T3	1		T5	14
valid_sources[0x6b]	54819	1			T1	129		T3	4		T5	6
valid_sources[0x6c]	56179	1			T1	116		T3	4		T5	17
valid_sources[0x6d]	52239	1			T1	113		T3	4		T5	5
valid_sources[0x6e]	54887	1			T1	137		T3	2		T5	5
valid_sources[0x6f]	52596	1			T1	133		T3	5		T5	7
valid_sources[0x70]	50814	1			T1	109		T3	5		T5	4
valid_sources[0x71]	55387	1			T1	126		T3	2		T5	8
valid_sources[0x72]	75917	1			T1	135		T3	1		T5	6
valid_sources[0x73]	58442	1			T1	116		T3	2		T5	2
valid_sources[0x74]	59356	1			T1	133		T3	1		T5	2
valid_sources[0x75]	91492	1			T1	115		T3	2		T5	2
valid_sources[0x76]	55580	1			T1	101		T3	2		T5	12
valid_sources[0x77]	53788	1			T1	124		T3	3		T5	4
valid_sources[0x78]	51584	1			T1	116		T3	1		T5	11
valid_sources[0x79]	54496	1			T1	125		T5	7		T4	16
valid_sources[0x7a]	51129	1			T1	120		T3	2		T5	12
valid_sources[0x7b]	101604	1			T1	136		T5	8		T4	8
valid_sources[0x7c]	52678	1			T1	122		T5	5		T4	19
valid_sources[0x7d]	51140	1			T1	99		T3	1		T5	7
valid_sources[0x7e]	50428	1			T1	135		T3	3		T5	10
valid_sources[0x7f]	50912	1			T1	121		T3	6		T5	7
valid_sources[0x80]	52805	1			T1	136		T5	2		T4	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3480478

1

T1

6055

T2

132

T3

282

values[0x0]

all_enables

biggest_size

1940641

1

T1

5358

T2

68

T3

25

values[0x1]

all_enables

biggest_size

1859624

1

T1

5122

T2

50

T3

12

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	252456	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

9169089

1

T1

28658

T3

40

T5

60

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2343008	1			T1	7189		T3	20		T5	30
values[0x0]	3438357	1			T1	10819		T3	10		T5	12
values[0x1]	3640180	1			T1	11401		T3	10		T5	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	90804	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9330741

1

T1

29147

T3

40

T5

60

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	37090	1			T1	116		T7	648		T8	731
valid_sources[0x01]	37566	1			T1	108		T100	2		T7	728
valid_sources[0x02]	35905	1			T1	123		T13	1		T100	1
valid_sources[0x03]	36605	1			T1	106		T13	2		T100	1
valid_sources[0x04]	36334	1			T1	108		T7	742		T8	708
valid_sources[0x05]	35740	1			T1	132		T3	1		T100	1
valid_sources[0x06]	36396	1			T1	112		T7	462		T8	798
valid_sources[0x07]	35625	1			T1	142		T6	2		T7	885
valid_sources[0x08]	36321	1			T1	116		T5	1		T7	758
valid_sources[0x09]	37780	1			T1	114		T7	438		T8	760
valid_sources[0x0a]	36725	1			T1	113		T7	616		T8	752
valid_sources[0x0b]	36365	1			T1	127		T100	1		T7	981
valid_sources[0x0c]	38909	1			T1	116		T100	2		T7	882
valid_sources[0x0d]	36160	1			T1	123		T100	1		T7	702
valid_sources[0x0e]	38121	1			T1	138		T7	514		T8	809
valid_sources[0x0f]	35675	1			T1	131		T5	1		T13	1
valid_sources[0x10]	37853	1			T1	114		T5	1		T6	1
valid_sources[0x11]	38230	1			T1	120		T13	1		T7	721
valid_sources[0x12]	36250	1			T1	114		T101	2		T7	998
valid_sources[0x13]	34961	1			T1	119		T101	3		T7	572
valid_sources[0x14]	36469	1			T1	134		T7	743		T8	759
valid_sources[0x15]	35484	1			T1	132		T13	2		T101	1
valid_sources[0x16]	37591	1			T1	121		T13	1		T100	1
valid_sources[0x17]	36535	1			T1	100		T7	583		T8	744
valid_sources[0x18]	38633	1			T1	105		T100	1		T7	703
valid_sources[0x19]	37791	1			T1	104		T5	2		T7	959
valid_sources[0x1a]	36827	1			T1	115		T5	2		T100	1
valid_sources[0x1b]	36139	1			T1	121		T13	1		T17	1
valid_sources[0x1c]	37629	1			T1	122		T7	498		T8	743
valid_sources[0x1d]	37934	1			T1	121		T24	14		T100	1
valid_sources[0x1e]	37490	1			T1	119		T5	1		T7	443
valid_sources[0x1f]	36728	1			T1	111		T5	1		T100	4
valid_sources[0x20]	35543	1			T1	99		T7	767		T8	724
valid_sources[0x21]	35174	1			T1	109		T7	530		T8	755
valid_sources[0x22]	39070	1			T1	125		T13	1		T7	946
valid_sources[0x23]	36205	1			T1	129		T5	1		T13	1
valid_sources[0x24]	37998	1			T1	126		T7	729		T8	725
valid_sources[0x25]	36410	1			T1	95		T7	620		T8	729
valid_sources[0x26]	36415	1			T1	123		T5	1		T24	27
valid_sources[0x27]	37506	1			T1	125		T13	1		T7	638
valid_sources[0x28]	35608	1			T1	93		T7	535		T8	709
valid_sources[0x29]	35289	1			T1	106		T3	1		T5	4
valid_sources[0x2a]	37121	1			T1	87		T7	695		T8	750
valid_sources[0x2b]	37124	1			T1	120		T7	779		T8	715
valid_sources[0x2c]	36286	1			T1	112		T5	1		T24	5
valid_sources[0x2d]	37446	1			T1	119		T5	1		T13	1
valid_sources[0x2e]	36329	1			T1	127		T13	1		T7	1116
valid_sources[0x2f]	35740	1			T1	129		T100	3		T7	779
valid_sources[0x30]	36747	1			T1	122		T13	1		T7	829
valid_sources[0x31]	37546	1			T1	111		T7	389		T8	818
valid_sources[0x32]	37006	1			T1	122		T7	739		T8	777
valid_sources[0x33]	37279	1			T1	100		T7	1044		T8	712
valid_sources[0x34]	33653	1			T1	128		T100	3		T7	813
valid_sources[0x35]	37125	1			T1	79		T5	1		T100	1
valid_sources[0x36]	36440	1			T1	120		T100	1		T7	738
valid_sources[0x37]	34123	1			T1	116		T13	1		T100	1
valid_sources[0x38]	36999	1			T1	105		T17	1		T100	2
valid_sources[0x39]	39003	1			T1	122		T5	1		T13	1
valid_sources[0x3a]	36431	1			T1	115		T7	817		T8	742
valid_sources[0x3b]	36295	1			T1	105		T100	1		T7	501
valid_sources[0x3c]	35085	1			T1	109		T5	1		T7	667
valid_sources[0x3d]	37399	1			T1	111		T5	2		T100	1
valid_sources[0x3e]	37051	1			T1	115		T7	489		T8	809
valid_sources[0x3f]	37511	1			T1	106		T4	160		T100	2
valid_sources[0x40]	38765	1			T1	128		T17	1		T7	1206
valid_sources[0x41]	36256	1			T1	98		T5	1		T13	1
valid_sources[0x42]	35986	1			T1	106		T5	2		T17	1
valid_sources[0x43]	36140	1			T1	123		T7	601		T8	739
valid_sources[0x44]	37893	1			T1	109		T13	1		T7	946
valid_sources[0x45]	36592	1			T1	130		T100	2		T7	691
valid_sources[0x46]	37008	1			T1	103		T13	1		T100	3
valid_sources[0x47]	37555	1			T1	116		T100	2		T7	911
valid_sources[0x48]	36833	1			T1	109		T7	734		T8	710
valid_sources[0x49]	35218	1			T1	102		T7	616		T8	707
valid_sources[0x4a]	36635	1			T1	94		T7	1070		T8	736
valid_sources[0x4b]	36003	1			T1	124		T7	578		T8	710
valid_sources[0x4c]	35840	1			T1	111		T3	1		T7	666
valid_sources[0x4d]	37843	1			T1	108		T13	1		T100	6
valid_sources[0x4e]	36574	1			T1	106		T13	1		T100	1
valid_sources[0x4f]	37591	1			T1	118		T7	868		T8	773
valid_sources[0x50]	37020	1			T1	125		T5	1		T6	1
valid_sources[0x51]	37051	1			T1	129		T100	4		T7	940
valid_sources[0x52]	34859	1			T1	128		T5	1		T13	1
valid_sources[0x53]	36182	1			T1	118		T13	1		T7	301
valid_sources[0x54]	37151	1			T1	120		T7	536		T8	752
valid_sources[0x55]	36401	1			T1	104		T7	1000		T8	740
valid_sources[0x56]	36900	1			T1	97		T100	2		T7	817
valid_sources[0x57]	36847	1			T1	113		T7	650		T8	690
valid_sources[0x58]	35891	1			T1	113		T7	833		T8	696
valid_sources[0x59]	35600	1			T1	100		T13	1		T18	3
valid_sources[0x5a]	37033	1			T1	118		T5	1		T7	533
valid_sources[0x5b]	37387	1			T1	101		T7	427		T8	720
valid_sources[0x5c]	37638	1			T1	130		T7	703		T8	710
valid_sources[0x5d]	38125	1			T1	115		T7	772		T8	744
valid_sources[0x5e]	37183	1			T1	110		T101	1		T7	489
valid_sources[0x5f]	37070	1			T1	110		T17	1		T100	1
valid_sources[0x60]	35903	1			T1	105		T7	865		T8	722
valid_sources[0x61]	36554	1			T1	132		T100	1		T7	839
valid_sources[0x62]	37049	1			T1	116		T5	4		T7	640
valid_sources[0x63]	36732	1			T1	126		T7	885		T8	735
valid_sources[0x64]	38272	1			T1	123		T7	832		T8	692
valid_sources[0x65]	35016	1			T1	125		T100	1		T7	821
valid_sources[0x66]	35712	1			T1	129		T5	1		T7	531
valid_sources[0x67]	37045	1			T1	111		T7	660		T8	725
valid_sources[0x68]	37399	1			T1	110		T13	2		T7	619
valid_sources[0x69]	36313	1			T1	128		T7	476		T8	714
valid_sources[0x6a]	39243	1			T1	108		T13	1		T100	1
valid_sources[0x6b]	35975	1			T1	108		T13	1		T7	816
valid_sources[0x6c]	37399	1			T1	117		T3	2		T24	11
valid_sources[0x6d]	37738	1			T1	104		T100	1		T7	770
valid_sources[0x6e]	37066	1			T1	119		T100	1		T7	883
valid_sources[0x6f]	37967	1			T1	112		T100	1		T7	825
valid_sources[0x70]	37038	1			T1	107		T13	1		T17	1
valid_sources[0x71]	37449	1			T1	102		T17	1		T7	979
valid_sources[0x72]	36851	1			T1	106		T5	1		T7	657
valid_sources[0x73]	37735	1			T1	128		T3	2		T7	360
valid_sources[0x74]	36507	1			T1	114		T6	1		T100	2
valid_sources[0x75]	37507	1			T1	116		T17	2		T7	838
valid_sources[0x76]	37104	1			T1	110		T7	753		T8	770
valid_sources[0x77]	37316	1			T1	120		T7	1078		T8	756
valid_sources[0x78]	37193	1			T1	111		T7	887		T8	796
valid_sources[0x79]	36249	1			T1	112		T7	587		T8	704
valid_sources[0x7a]	36965	1			T1	130		T100	1		T7	1123
valid_sources[0x7b]	34762	1			T1	121		T7	626		T8	750
valid_sources[0x7c]	37616	1			T1	100		T7	827		T8	718
valid_sources[0x7d]	37692	1			T1	139		T7	1144		T8	755
valid_sources[0x7e]	37319	1			T1	114		T17	2		T100	1
valid_sources[0x7f]	36891	1			T1	111		T7	690		T8	720
valid_sources[0x80]	38233	1			T1	119		T100	2		T7	731

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2329599

1

T1

7175

T3

20

T5

30

values[0x0]

all_enables

biggest_size

3421104

1

T1

10770

T3

10

T5

12

values[0x1]

all_enables

biggest_size

3418386

1

T1

10713

T3

10

T5

18