Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

25638458

1

T1

70890

T2

1022

T3

487

full_word

8381018

1

T1

19951

T2

250

T3

319

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34019196	1			T1	90841		T2	1272		T3	806
auto[TlIntgErrCmd]	98	1			T265	4		T266	5		T267	3
auto[TlIntgErrData]	90	1			T265	3		T266	1		T267	3
auto[TlIntgErrBoth]	92	1			T265	3		T266	4		T267	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9933811

1

T1

19068

T2

988

T3

718

auto[1]

24085665

1

T1

71773

T2

284

T3

88

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6317585	1			T1	12594		T2	856		T3	436
auto[TlIntgErrNone]	partial	auto[1]	19320614	1			T1	58296		T2	166		T3	51
auto[TlIntgErrNone]	full_word	auto[0]	3616080	1			T1	6474		T2	132		T3	282
auto[TlIntgErrNone]	full_word	auto[1]	4764917	1			T1	13477		T2	118		T3	37
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T265	1		T266	1		T267	1
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T265	2		T266	3		T267	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T265	1		T353	1		T270	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T266	1		T267	1		T273	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T265	2		T267	2		T273	3
auto[TlIntgErrData]	partial	auto[1]	35	1			T265	1		T266	1		T267	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T353	1		T352	1		T272	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T353	1		T355	1		T356	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T265	1		T266	3		T267	3
auto[TlIntgErrBoth]	partial	auto[1]	42	1			T265	2		T266	1		T267	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T352	1		T272	1		T270	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T350	1		T357	1		T272	1