Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 91.67 100.00 100.00 100.00 100.00 u_otp_ctrl_scrmbl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 91.67 100.00 100.00 100.00 100.00 u_otp_ctrl_scrmbl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_present ( parameter DataWidth=64,KeyWidth=128,NumRounds=31,NumPhysRounds=1,Decrypt=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc

Line No.TotalCoveredPercent
TOTAL1111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6911100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN12311100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
63 1 1
64 1 1
69 1 1
106 1 1
109 1 1
111 1 1
123 1 1
139 1 1
144 1 1
145 1 1


Line Coverage for Module : prim_present ( parameter DataWidth=64,KeyWidth=128,NumRounds=31,NumPhysRounds=1,Decrypt=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec

Line No.TotalCoveredPercent
TOTAL1111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6911100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN9111100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
63 1 1
64 1 1
69 1 1
74 1 1
77 1 1
79 1 1
91 1 1
139 1 1
144 1 1
145 1 1


Cond Coverage for Module : prim_present
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       139
 EXPRESSION 
 Number  Term
      1  (int'(idx_o) == LastRoundIdx) ? ((data_state[NumPhysRounds] ^ round_key[NumPhysRounds][(KeyWidth - 1):(KeyWidth - DataWidth)])) : data_state[NumPhysRounds])
-1-StatusTests
0UnreachableT1,T2,T3
1CoveredT1,T2,T3

 LINE       139
 SUB-EXPRESSION (int'(idx_o) == LastRoundIdx)
                --------------1--------------
-1-StatusTests
0UnreachableT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : prim_present
Line No.TotalCoveredPercent
Branches 1 1 100.00
TERNARY 139 1 1 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 139 ((int'(idx_o) == LastRoundIdx)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable T1,T2,T3


Assert Coverage for Module : prim_present
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SupportedNumPhysRounds0_A 2302 2302 0 0
SupportedNumPhysRounds1_A 2302 2302 0 0
SupportedNumRounds_A 2302 2302 0 0
SupportedWidths_A 2302 2302 0 0


SupportedNumPhysRounds0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2302 2302 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T13 2 2 0 0
T14 2 2 0 0
T15 2 2 0 0
T16 2 2 0 0

SupportedNumPhysRounds1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2302 2302 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T13 2 2 0 0
T14 2 2 0 0
T15 2 2 0 0
T16 2 2 0 0

SupportedNumRounds_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2302 2302 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T13 2 2 0 0
T14 2 2 0 0
T15 2 2 0 0
T16 2 2 0 0

SupportedWidths_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2302 2302 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T13 2 2 0 0
T14 2 2 0 0
T15 2 2 0 0
T16 2 2 0 0

Line Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc
Line No.TotalCoveredPercent
TOTAL1111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6911100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN12311100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
63 1 1
64 1 1
69 1 1
106 1 1
109 1 1
111 1 1
123 1 1
139 1 1
144 1 1
145 1 1


Cond Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       139
 EXPRESSION 
 Number  Term
      1  (int'(idx_o) == LastRoundIdx) ? ((data_state[NumPhysRounds] ^ round_key[NumPhysRounds][(KeyWidth - 1):(KeyWidth - DataWidth)])) : data_state[NumPhysRounds])
-1-StatusTests
0UnreachableT1,T2,T3
1CoveredT1,T2,T3

 LINE       139
 SUB-EXPRESSION (int'(idx_o) == LastRoundIdx)
                --------------1--------------
-1-StatusTests
0UnreachableT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc
Line No.TotalCoveredPercent
Branches 1 1 100.00
TERNARY 139 1 1 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 139 ((int'(idx_o) == LastRoundIdx)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable T1,T2,T3


Assert Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SupportedNumPhysRounds0_A 1151 1151 0 0
SupportedNumPhysRounds1_A 1151 1151 0 0
SupportedNumRounds_A 1151 1151 0 0
SupportedWidths_A 1151 1151 0 0


SupportedNumPhysRounds0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1151 1151 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0

SupportedNumPhysRounds1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1151 1151 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0

SupportedNumRounds_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1151 1151 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0

SupportedWidths_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1151 1151 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0

Line Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec
Line No.TotalCoveredPercent
TOTAL1111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6911100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN9111100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
63 1 1
64 1 1
69 1 1
74 1 1
77 1 1
79 1 1
91 1 1
139 1 1
144 1 1
145 1 1


Cond Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       139
 EXPRESSION 
 Number  Term
      1  (int'(idx_o) == LastRoundIdx) ? ((data_state[NumPhysRounds] ^ round_key[NumPhysRounds][(KeyWidth - 1):(KeyWidth - DataWidth)])) : data_state[NumPhysRounds])
-1-StatusTests
0UnreachableT1,T2,T3
1CoveredT1,T2,T3

 LINE       139
 SUB-EXPRESSION (int'(idx_o) == LastRoundIdx)
                --------------1--------------
-1-StatusTests
0UnreachableT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec
Line No.TotalCoveredPercent
Branches 1 1 100.00
TERNARY 139 1 1 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 139 ((int'(idx_o) == LastRoundIdx)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable T1,T2,T3


Assert Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SupportedNumPhysRounds0_A 1151 1151 0 0
SupportedNumPhysRounds1_A 1151 1151 0 0
SupportedNumRounds_A 1151 1151 0 0
SupportedWidths_A 1151 1151 0 0


SupportedNumPhysRounds0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1151 1151 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0

SupportedNumPhysRounds1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1151 1151 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0

SupportedNumRounds_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1151 1151 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0

SupportedWidths_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1151 1151 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%