Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7052332	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7108918

1

T1

204

T2

1461

T3

34

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8119178	1			T1	1222		T2	2715		T3	1
values[0x0]	2303912	1			T1	113		T2	484		T3	47
values[0x1]	3738160	1			T1	125		T2	475		T3	53

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4564248	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9597002

1

T1

577

T2

1985

T3

41

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	49885	1			T1	10		T2	11		T8	3
valid_sources[0x01]	51429	1			T1	2		T2	19		T8	8
valid_sources[0x02]	52088	1			T2	8		T7	8		T4	6
valid_sources[0x03]	53036	1			T2	6		T7	6		T4	7
valid_sources[0x04]	53725	1			T2	26		T7	2		T4	5
valid_sources[0x05]	55289	1			T1	2		T2	19		T7	2
valid_sources[0x06]	61928	1			T2	13		T4	8		T5	630
valid_sources[0x07]	53404	1			T1	12		T2	10		T8	3
valid_sources[0x08]	50710	1			T1	27		T2	23		T4	16
valid_sources[0x09]	53911	1			T1	9		T2	25		T7	5
valid_sources[0x0a]	72073	1			T1	5		T2	35		T8	16
valid_sources[0x0b]	50475	1			T1	7		T2	10		T3	1
valid_sources[0x0c]	53609	1			T2	6		T8	7		T7	6
valid_sources[0x0d]	48656	1			T2	17		T7	3		T4	7
valid_sources[0x0e]	55250	1			T2	13		T7	4		T4	6
valid_sources[0x0f]	59041	1			T1	6		T2	8		T7	2
valid_sources[0x10]	49990	1			T2	10		T7	4		T4	8
valid_sources[0x11]	50975	1			T2	25		T7	2		T4	3
valid_sources[0x12]	50005	1			T1	25		T2	1		T3	4
valid_sources[0x13]	56021	1			T1	20		T2	5		T7	3
valid_sources[0x14]	59372	1			T1	7		T2	12		T7	2
valid_sources[0x15]	49901	1			T1	5		T2	30		T7	5
valid_sources[0x16]	48887	1			T1	25		T2	19		T7	6
valid_sources[0x17]	49376	1			T1	11		T2	7		T8	9
valid_sources[0x18]	66288	1			T1	17		T2	5		T7	2
valid_sources[0x19]	53265	1			T1	6		T2	16		T7	2
valid_sources[0x1a]	55751	1			T2	7		T7	9		T4	11
valid_sources[0x1b]	50979	1			T2	15		T7	1		T4	3
valid_sources[0x1c]	54291	1			T2	10		T7	5		T4	5
valid_sources[0x1d]	48656	1			T1	16		T2	29		T7	4
valid_sources[0x1e]	60560	1			T1	16		T2	9		T8	1
valid_sources[0x1f]	50894	1			T1	1		T2	19		T8	4
valid_sources[0x20]	53739	1			T1	13		T2	2		T3	6
valid_sources[0x21]	49141	1			T2	27		T8	11		T7	4
valid_sources[0x22]	48890	1			T1	7		T2	32		T7	4
valid_sources[0x23]	50727	1			T1	3		T2	21		T8	2
valid_sources[0x24]	54835	1			T1	6		T2	14		T7	6
valid_sources[0x25]	54372	1			T1	7		T2	11		T8	1
valid_sources[0x26]	51624	1			T2	17		T7	6		T4	1
valid_sources[0x27]	54029	1			T1	4		T2	8		T8	3
valid_sources[0x28]	50813	1			T1	2		T2	6		T8	17
valid_sources[0x29]	47790	1			T2	17		T7	9		T4	4
valid_sources[0x2a]	56272	1			T2	17		T8	14		T7	2
valid_sources[0x2b]	52757	1			T1	1		T2	22		T3	1
valid_sources[0x2c]	48729	1			T1	6		T2	15		T8	14
valid_sources[0x2d]	49481	1			T1	22		T2	10		T7	4
valid_sources[0x2e]	61426	1			T1	5		T2	13		T8	4
valid_sources[0x2f]	50273	1			T1	4		T2	7		T7	4
valid_sources[0x30]	52005	1			T1	22		T2	7		T7	6
valid_sources[0x31]	53136	1			T1	5		T2	16		T7	11
valid_sources[0x32]	48035	1			T2	6		T8	6		T7	5
valid_sources[0x33]	54607	1			T1	6		T2	4		T7	1
valid_sources[0x34]	55519	1			T2	24		T7	4		T4	9
valid_sources[0x35]	63493	1			T1	4		T2	12		T7	1
valid_sources[0x36]	53753	1			T1	13		T2	14		T7	3
valid_sources[0x37]	57665	1			T1	21		T2	19		T7	7
valid_sources[0x38]	53916	1			T1	1		T2	35		T8	15
valid_sources[0x39]	58032	1			T1	7		T2	10		T7	3
valid_sources[0x3a]	55576	1			T1	12		T2	11		T3	2
valid_sources[0x3b]	59853	1			T1	12		T2	30		T8	21
valid_sources[0x3c]	58658	1			T1	1		T2	17		T7	7
valid_sources[0x3d]	49683	1			T8	3		T7	1		T4	10
valid_sources[0x3e]	52505	1			T1	15		T2	8		T7	4
valid_sources[0x3f]	53431	1			T2	18		T7	5		T4	5
valid_sources[0x40]	54351	1			T1	2		T2	12		T8	1
valid_sources[0x41]	50657	1			T1	8		T2	6		T7	2
valid_sources[0x42]	52529	1			T2	8		T3	3		T8	36
valid_sources[0x43]	52606	1			T1	12		T2	8		T8	4
valid_sources[0x44]	65334	1			T1	3		T2	13		T7	15
valid_sources[0x45]	49320	1			T1	8		T2	14		T7	5
valid_sources[0x46]	63737	1			T1	11		T2	18		T8	9
valid_sources[0x47]	65879	1			T1	13		T2	6		T7	3
valid_sources[0x48]	52961	1			T1	1		T2	2		T8	74
valid_sources[0x49]	49249	1			T1	4		T2	5		T7	7
valid_sources[0x4a]	53992	1			T1	6		T2	12		T7	6
valid_sources[0x4b]	50198	1			T1	8		T2	19		T8	16
valid_sources[0x4c]	60114	1			T2	18		T8	1		T7	1
valid_sources[0x4d]	50105	1			T2	12		T8	19		T7	3
valid_sources[0x4e]	53700	1			T1	7		T2	13		T7	5
valid_sources[0x4f]	51816	1			T1	6		T2	15		T7	6
valid_sources[0x50]	49223	1			T1	3		T2	40		T7	3
valid_sources[0x51]	54665	1			T1	10		T2	22		T8	1
valid_sources[0x52]	57043	1			T2	21		T8	6		T7	9
valid_sources[0x53]	56503	1			T1	1		T2	23		T8	64
valid_sources[0x54]	61915	1			T1	4		T2	21		T4	9
valid_sources[0x55]	53810	1			T2	1		T7	3		T4	11
valid_sources[0x56]	50456	1			T1	1		T2	29		T3	2
valid_sources[0x57]	51139	1			T1	9		T2	11		T7	10
valid_sources[0x58]	57263	1			T1	2		T2	5		T7	5
valid_sources[0x59]	56987	1			T1	2		T2	14		T7	3
valid_sources[0x5a]	51757	1			T1	10		T2	13		T7	10
valid_sources[0x5b]	51222	1			T2	7		T3	2		T8	1
valid_sources[0x5c]	64588	1			T1	6		T2	11		T7	2
valid_sources[0x5d]	51486	1			T1	9		T2	34		T7	3
valid_sources[0x5e]	51462	1			T1	6		T2	48		T8	1
valid_sources[0x5f]	50064	1			T2	4		T4	5		T5	252
valid_sources[0x60]	54468	1			T1	6		T2	13		T7	7
valid_sources[0x61]	51103	1			T1	8		T2	10		T7	6
valid_sources[0x62]	51978	1			T2	15		T7	1		T4	7
valid_sources[0x63]	49629	1			T1	7		T2	4		T8	10
valid_sources[0x64]	52625	1			T1	17		T2	9		T3	4
valid_sources[0x65]	52368	1			T2	5		T7	3		T4	8
valid_sources[0x66]	52173	1			T1	27		T2	9		T7	1
valid_sources[0x67]	52373	1			T1	19		T2	11		T8	18
valid_sources[0x68]	58619	1			T1	14		T2	51		T8	6
valid_sources[0x69]	64704	1			T1	12		T2	8		T7	6
valid_sources[0x6a]	47952	1			T1	6		T2	26		T3	13
valid_sources[0x6b]	57257	1			T1	9		T2	24		T8	19
valid_sources[0x6c]	54156	1			T1	1		T2	6		T8	28
valid_sources[0x6d]	50330	1			T1	5		T2	17		T8	9
valid_sources[0x6e]	65341	1			T1	29		T2	3		T7	5
valid_sources[0x6f]	50210	1			T2	16		T7	5		T4	10
valid_sources[0x70]	49977	1			T2	19		T8	27		T7	12
valid_sources[0x71]	58206	1			T1	4		T2	7		T7	5
valid_sources[0x72]	60556	1			T1	7		T2	25		T7	8
valid_sources[0x73]	49836	1			T2	9		T7	5		T4	7
valid_sources[0x74]	48316	1			T2	13		T3	15		T7	2
valid_sources[0x75]	61985	1			T1	6		T2	30		T7	4
valid_sources[0x76]	52018	1			T1	10		T2	5		T7	7
valid_sources[0x77]	57919	1			T1	1		T2	15		T8	10
valid_sources[0x78]	47683	1			T1	6		T2	14		T7	6
valid_sources[0x79]	56804	1			T1	7		T2	20		T7	8
valid_sources[0x7a]	47832	1			T1	2		T2	17		T8	1
valid_sources[0x7b]	53854	1			T2	7		T8	3		T7	5
valid_sources[0x7c]	49458	1			T1	4		T7	2		T4	9
valid_sources[0x7d]	59754	1			T1	7		T2	1		T8	36
valid_sources[0x7e]	51691	1			T2	18		T7	5		T4	7
valid_sources[0x7f]	50408	1			T1	10		T2	28		T7	5
valid_sources[0x80]	55732	1			T1	2		T2	19		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3374514

1

T1

102

T2

1073

T8

210

values[0x0]

all_enables

biggest_size

1906255

1

T1

65

T2

235

T3

22

values[0x1]

all_enables

biggest_size

1828149

1

T1

37

T2

153

T3

12

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	248284	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8943853

1

T2

220

T8

80

T4

40

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2286601	1			T2	110		T8	40		T4	20
values[0x0]	3352254	1			T2	59		T8	21		T4	12
values[0x1]	3553282	1			T2	51		T8	19		T4	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	89214	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9102923

1

T2

220

T8

80

T4

40

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	37257	1			T2	2		T5	301		T55	4
valid_sources[0x01]	36723	1			T2	1		T5	302		T10	3
valid_sources[0x02]	34772	1			T5	287		T12	160		T55	69
valid_sources[0x03]	37775	1			T5	291		T10	3		T183	20
valid_sources[0x04]	36152	1			T5	313		T9	37		T107	1
valid_sources[0x05]	35880	1			T5	335		T107	1		T10	5
valid_sources[0x06]	36953	1			T2	1		T5	345		T37	1
valid_sources[0x07]	35787	1			T5	301		T37	2		T10	2
valid_sources[0x08]	37366	1			T2	1		T5	318		T9	3
valid_sources[0x09]	35425	1			T2	1		T5	314		T10	6
valid_sources[0x0a]	36239	1			T5	318		T107	1		T10	2
valid_sources[0x0b]	35207	1			T2	2		T5	293		T30	140
valid_sources[0x0c]	35939	1			T5	292		T9	7		T10	3
valid_sources[0x0d]	35911	1			T2	2		T5	308		T10	1
valid_sources[0x0e]	34432	1			T2	1		T5	299		T9	13
valid_sources[0x0f]	34606	1			T5	321		T10	2		T31	1
valid_sources[0x10]	36238	1			T5	316		T10	3		T110	1
valid_sources[0x11]	35326	1			T5	292		T37	1		T9	25
valid_sources[0x12]	36701	1			T2	2		T5	318		T9	12
valid_sources[0x13]	36615	1			T2	2		T5	319		T55	6
valid_sources[0x14]	35857	1			T2	1		T5	290		T10	2
valid_sources[0x15]	36335	1			T2	1		T5	333		T37	1
valid_sources[0x16]	36366	1			T2	1		T5	320		T55	4
valid_sources[0x17]	35093	1			T5	323		T107	1		T10	6
valid_sources[0x18]	35692	1			T5	299		T109	1		T111	1
valid_sources[0x19]	37933	1			T5	313		T10	3		T109	1
valid_sources[0x1a]	35173	1			T2	1		T5	291		T9	11
valid_sources[0x1b]	35482	1			T5	297		T11	1		T10	5
valid_sources[0x1c]	35926	1			T2	1		T5	270		T37	1
valid_sources[0x1d]	34879	1			T5	301		T6	1		T9	4
valid_sources[0x1e]	36947	1			T5	303		T55	18		T37	2
valid_sources[0x1f]	35172	1			T5	303		T10	4		T109	1
valid_sources[0x20]	35599	1			T2	1		T5	314		T107	2
valid_sources[0x21]	35142	1			T5	348		T107	1		T10	4
valid_sources[0x22]	34643	1			T5	303		T9	3		T107	1
valid_sources[0x23]	37158	1			T2	2		T5	320		T9	1
valid_sources[0x24]	37116	1			T2	3		T5	314		T107	1
valid_sources[0x25]	35689	1			T5	327		T9	2		T10	3
valid_sources[0x26]	36439	1			T2	1		T5	309		T9	6
valid_sources[0x27]	36652	1			T5	295		T55	15		T10	4
valid_sources[0x28]	37097	1			T2	1		T5	303		T9	7
valid_sources[0x29]	35646	1			T2	2		T8	4		T5	276
valid_sources[0x2a]	36289	1			T2	1		T5	323		T9	4
valid_sources[0x2b]	36132	1			T2	1		T8	3		T5	270
valid_sources[0x2c]	36686	1			T2	1		T5	286		T107	1
valid_sources[0x2d]	35341	1			T2	1		T5	312		T37	1
valid_sources[0x2e]	35435	1			T5	340		T9	3		T10	2
valid_sources[0x2f]	35178	1			T2	2		T5	322		T107	1
valid_sources[0x30]	35806	1			T5	279		T9	4		T10	4
valid_sources[0x31]	37658	1			T2	2		T5	280		T37	1
valid_sources[0x32]	36137	1			T2	2		T5	301		T10	5
valid_sources[0x33]	34676	1			T2	3		T5	309		T9	6
valid_sources[0x34]	35895	1			T5	308		T10	4		T109	1
valid_sources[0x35]	35388	1			T2	1		T5	289		T10	4
valid_sources[0x36]	34531	1			T2	1		T5	286		T55	1
valid_sources[0x37]	36406	1			T2	3		T5	302		T107	2
valid_sources[0x38]	33833	1			T5	287		T9	2		T10	1
valid_sources[0x39]	34021	1			T5	316		T107	1		T10	2
valid_sources[0x3a]	35491	1			T5	289		T37	1		T107	3
valid_sources[0x3b]	33712	1			T2	1		T5	304		T10	6
valid_sources[0x3c]	35977	1			T2	1		T5	304		T10	7
valid_sources[0x3d]	36555	1			T5	282		T10	5		T109	1
valid_sources[0x3e]	36026	1			T2	2		T5	290		T37	2
valid_sources[0x3f]	38437	1			T5	304		T6	1		T10	4
valid_sources[0x40]	35591	1			T2	1		T5	336		T55	4
valid_sources[0x41]	35050	1			T5	327		T10	5		T82	2
valid_sources[0x42]	36371	1			T5	324		T9	9		T107	1
valid_sources[0x43]	33776	1			T2	1		T5	311		T37	1
valid_sources[0x44]	36791	1			T2	1		T5	319		T9	9
valid_sources[0x45]	36077	1			T2	1		T5	317		T10	3
valid_sources[0x46]	34232	1			T2	1		T5	327		T9	28
valid_sources[0x47]	36273	1			T2	1		T5	319		T10	1
valid_sources[0x48]	35660	1			T2	1		T5	307		T107	1
valid_sources[0x49]	36994	1			T2	1		T5	301		T10	1
valid_sources[0x4a]	36523	1			T5	296		T10	4		T82	4
valid_sources[0x4b]	36761	1			T2	2		T5	285		T10	4
valid_sources[0x4c]	36210	1			T5	324		T37	1		T107	1
valid_sources[0x4d]	36806	1			T5	332		T10	1		T109	1
valid_sources[0x4e]	34112	1			T2	1		T5	318		T9	3
valid_sources[0x4f]	34161	1			T2	2		T5	285		T10	2
valid_sources[0x50]	35756	1			T2	1		T5	318		T10	2
valid_sources[0x51]	34614	1			T2	2		T8	13		T5	325
valid_sources[0x52]	34494	1			T5	308		T9	14		T10	6
valid_sources[0x53]	36315	1			T2	1		T5	288		T37	1
valid_sources[0x54]	36411	1			T2	1		T5	280		T10	1
valid_sources[0x55]	35819	1			T2	1		T5	298		T9	11
valid_sources[0x56]	36835	1			T2	1		T5	319		T82	1
valid_sources[0x57]	36197	1			T5	305		T107	1		T10	9
valid_sources[0x58]	34441	1			T2	1		T5	295		T107	1
valid_sources[0x59]	36846	1			T2	1		T8	3		T5	318
valid_sources[0x5a]	35774	1			T5	312		T10	5		T113	1
valid_sources[0x5b]	37652	1			T2	2		T5	317		T55	11
valid_sources[0x5c]	35900	1			T2	1		T5	335		T107	2
valid_sources[0x5d]	38183	1			T2	1		T5	292		T9	18
valid_sources[0x5e]	36307	1			T2	1		T5	323		T10	2
valid_sources[0x5f]	35103	1			T2	2		T5	341		T9	3
valid_sources[0x60]	36719	1			T5	281		T9	4		T107	1
valid_sources[0x61]	34999	1			T5	289		T10	7		T102	1
valid_sources[0x62]	35571	1			T5	294		T55	2		T10	9
valid_sources[0x63]	36582	1			T5	318		T107	6		T10	9
valid_sources[0x64]	35854	1			T2	1		T5	296		T10	1
valid_sources[0x65]	35378	1			T5	305		T9	9		T107	1
valid_sources[0x66]	33698	1			T2	2		T5	314		T9	4
valid_sources[0x67]	36445	1			T2	1		T5	293		T9	17
valid_sources[0x68]	35790	1			T2	1		T5	325		T10	1
valid_sources[0x69]	36721	1			T2	1		T5	338		T9	8
valid_sources[0x6a]	38206	1			T2	4		T5	309		T107	2
valid_sources[0x6b]	36330	1			T2	1		T5	337		T55	3
valid_sources[0x6c]	35357	1			T2	1		T5	311		T9	5
valid_sources[0x6d]	36001	1			T5	315		T10	10		T114	2
valid_sources[0x6e]	36338	1			T2	2		T5	306		T10	4
valid_sources[0x6f]	34818	1			T2	2		T5	291		T10	5
valid_sources[0x70]	36011	1			T2	1		T5	298		T10	3
valid_sources[0x71]	36683	1			T5	298		T55	2		T10	4
valid_sources[0x72]	37817	1			T5	305		T10	3		T114	2
valid_sources[0x73]	36791	1			T5	269		T10	6		T113	4
valid_sources[0x74]	36044	1			T2	3		T5	311		T107	1
valid_sources[0x75]	34901	1			T2	1		T5	293		T10	4
valid_sources[0x76]	36396	1			T2	1		T5	272		T10	4
valid_sources[0x77]	36757	1			T2	3		T5	327		T10	3
valid_sources[0x78]	35579	1			T5	285		T10	3		T109	3
valid_sources[0x79]	36950	1			T5	294		T10	6		T113	3
valid_sources[0x7a]	34298	1			T2	1		T5	294		T10	4
valid_sources[0x7b]	35005	1			T5	326		T55	6		T37	1
valid_sources[0x7c]	35563	1			T5	294		T11	19		T10	4
valid_sources[0x7d]	34577	1			T2	1		T5	307		T107	1
valid_sources[0x7e]	34899	1			T2	2		T5	292		T10	3
valid_sources[0x7f]	37277	1			T2	1		T5	290		T9	1
valid_sources[0x80]	38103	1			T5	342		T10	1		T103	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2273110

1

T2

110

T8

40

T4

20

values[0x0]

all_enables

biggest_size

3335216

1

T2

59

T8

21

T4

12

values[0x1]

all_enables

biggest_size

3335527

1

T2

51

T8

19

T4

8