Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

24887728

1

T1

1256

T2

2213

T3

67

full_word

8189166

1

T1

204

T2

1461

T3

34

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33076614	1			T1	1460		T2	3674		T3	101
auto[TlIntgErrCmd]	94	1			T282	5		T283	3		T284	6
auto[TlIntgErrData]	98	1			T282	9		T283	4		T284	3
auto[TlIntgErrBoth]	88	1			T282	6		T283	3		T284	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9425996

1

T1

1222

T2

2715

T3

1

auto[1]

23650898

1

T1

238

T2

959

T3

100

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5919036	1			T1	1120		T2	1642		T3	1
auto[TlIntgErrNone]	partial	auto[1]	18968432	1			T1	136		T2	571		T3	66
auto[TlIntgErrNone]	full_word	auto[0]	3506832	1			T1	102		T2	1073		T8	210
auto[TlIntgErrNone]	full_word	auto[1]	4682314	1			T1	102		T2	388		T3	34
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T282	4		T283	1		T284	3
auto[TlIntgErrCmd]	partial	auto[1]	40	1			T282	1		T283	1		T284	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T360	1		T361	1		T362	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T283	1		T354	1		T363	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T282	1		T283	2		T284	3
auto[TlIntgErrData]	partial	auto[1]	49	1			T282	7		T283	2		T360	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T282	1		T360	1		T364	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T358	1		T354	1		T355	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T282	1		T283	2		T284	1
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T282	4		T283	1		T290	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T363	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T282	1		T363	1		T356	1