Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.18		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	468606785	8028005	0	0
check_regwen_rd_A	468606785	4528	0	0
check_timeout_rd_A	468606785	3451	0	0
check_trigger_regwen_rd_A	468606785	4493	0	0
consistency_check_period_rd_A	468606785	4714	0	0
creator_sw_cfg_read_lock_rd_A	468606785	3665	0	0
direct_access_address_rd_A	468606785	2909	0	0
direct_access_wdata_0_rd_A	468606785	1763	0	0
direct_access_wdata_1_rd_A	468606785	2298	0	0
integrity_check_period_rd_A	468606785	4675	0	0
intr_enable_rd_A	468606785	5604	0	0
owner_sw_cfg_read_lock_rd_A	468606785	3292	0	0
rot_creator_auth_codesign_read_lock_rd_A	468606785	3767	0	0
rot_creator_auth_state_read_lock_rd_A	468606785	3500	0	0
vendor_test_read_lock_rd_A	468606785	3225	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468606785	8028005	0	0
T5	354836	64245	0	0
T6	15655	0	0	0
T9	849199	0	0	0
T11	12415	0	0	0
T12	19430	0	0	0
T13	0	152641	0	0
T14	0	310592	0	0
T17	4113	0	0	0
T18	0	52899	0	0
T19	0	34848	0	0
T20	0	37181	0	0
T30	61764	0	0	0
T37	18164	0	0	0
T55	17937	0	0	0
T74	14431	0	0	0
T246	0	54686	0	0
T253	0	168728	0	0
T276	0	70703	0	0
T292	0	160295	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468606785	4528	0	0
T5	354836	102	0	0
T6	15655	0	0	0
T9	849199	0	0	0
T11	12415	0	0	0
T12	19430	0	0	0
T17	4113	0	0	0
T19	0	58	0	0
T20	0	29	0	0
T21	0	89	0	0
T30	61764	0	0	0
T37	18164	0	0	0
T55	17937	0	0	0
T74	14431	0	0	0
T227	0	104	0	0
T276	0	92	0	0
T337	0	50	0	0
T338	0	98	0	0
T339	0	61	0	0
T340	0	37	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468606785	3451	0	0
T5	354836	115	0	0
T6	15655	0	0	0
T9	849199	0	0	0
T11	12415	0	0	0
T12	19430	0	0	0
T17	4113	0	0	0
T19	0	34	0	0
T20	0	23	0	0
T21	0	121	0	0
T30	61764	0	0	0
T37	18164	0	0	0
T55	17937	0	0	0
T74	14431	0	0	0
T227	0	125	0	0
T276	0	123	0	0
T337	0	37	0	0
T338	0	95	0	0
T339	0	59	0	0
T340	0	40	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468606785	4493	0	0
T5	354836	127	0	0
T6	15655	0	0	0
T9	849199	0	0	0
T11	12415	0	0	0
T12	19430	0	0	0
T17	4113	0	0	0
T19	0	51	0	0
T20	0	52	0	0
T21	0	109	0	0
T30	61764	0	0	0
T37	18164	0	0	0
T55	17937	0	0	0
T74	14431	0	0	0
T227	0	120	0	0
T276	0	83	0	0
T337	0	35	0	0
T338	0	110	0	0
T339	0	47	0	0
T340	0	39	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468606785	4714	0	0
T5	354836	118	0	0
T6	15655	0	0	0
T9	849199	0	0	0
T11	12415	0	0	0
T12	19430	0	0	0
T17	4113	0	0	0
T19	0	37	0	0
T20	0	28	0	0
T21	0	122	0	0
T30	61764	0	0	0
T37	18164	0	0	0
T55	17937	0	0	0
T74	14431	0	0	0
T227	0	113	0	0
T276	0	93	0	0
T337	0	44	0	0
T338	0	169	0	0
T339	0	63	0	0
T340	0	60	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468606785	3665	0	0
T5	354836	96	0	0
T6	15655	0	0	0
T9	849199	0	0	0
T11	12415	0	0	0
T12	19430	0	0	0
T17	4113	0	0	0
T19	0	41	0	0
T20	0	30	0	0
T21	0	166	0	0
T30	61764	0	0	0
T37	18164	0	0	0
T55	17937	0	0	0
T74	14431	0	0	0
T227	0	103	0	0
T276	0	87	0	0
T337	0	29	0	0
T338	0	143	0	0
T339	0	68	0	0
T340	0	45	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468606785	2909	0	0
T5	354836	145	0	0
T6	15655	0	0	0
T9	849199	0	0	0
T11	12415	0	0	0
T12	19430	0	0	0
T17	4113	0	0	0
T19	0	25	0	0
T20	0	39	0	0
T21	0	116	0	0
T30	61764	0	0	0
T37	18164	0	0	0
T55	17937	0	0	0
T74	14431	0	0	0
T227	0	110	0	0
T276	0	110	0	0
T337	0	29	0	0
T338	0	149	0	0
T339	0	61	0	0
T340	0	50	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468606785	1763	0	0
T5	354836	64	0	0
T6	15655	0	0	0
T9	849199	0	0	0
T11	12415	0	0	0
T12	19430	0	0	0
T17	4113	0	0	0
T19	0	25	0	0
T20	0	14	0	0
T21	0	84	0	0
T30	61764	0	0	0
T37	18164	0	0	0
T55	17937	0	0	0
T74	14431	0	0	0
T227	0	105	0	0
T276	0	34	0	0
T337	0	35	0	0
T338	0	86	0	0
T339	0	26	0	0
T340	0	23	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468606785	2298	0	0
T5	354836	41	0	0
T6	15655	0	0	0
T9	849199	0	0	0
T11	12415	0	0	0
T12	19430	0	0	0
T17	4113	0	0	0
T19	0	28	0	0
T20	0	16	0	0
T21	0	97	0	0
T30	61764	0	0	0
T37	18164	0	0	0
T55	17937	0	0	0
T74	14431	0	0	0
T227	0	95	0	0
T276	0	88	0	0
T337	0	19	0	0
T338	0	88	0	0
T339	0	34	0	0
T340	0	29	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468606785	4675	0	0
T5	354836	93	0	0
T6	15655	0	0	0
T9	849199	0	0	0
T11	12415	0	0	0
T12	19430	0	0	0
T17	4113	0	0	0
T19	0	69	0	0
T20	0	26	0	0
T21	0	147	0	0
T30	61764	0	0	0
T37	18164	0	0	0
T55	17937	0	0	0
T74	14431	0	0	0
T227	0	135	0	0
T276	0	75	0	0
T337	0	20	0	0
T338	0	119	0	0
T339	0	104	0	0
T340	0	64	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468606785	5604	0	0
T5	354836	96	0	0
T6	15655	0	0	0
T9	849199	18	0	0
T11	12415	0	0	0
T12	19430	0	0	0
T17	4113	0	0	0
T19	0	83	0	0
T20	0	34	0	0
T30	61764	0	0	0
T37	18164	0	0	0
T55	17937	0	0	0
T74	14431	0	0	0
T129	0	10	0	0
T254	0	34	0	0
T255	0	22	0	0
T276	0	160	0	0
T337	0	31	0	0
T338	0	154	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468606785	3292	0	0
T5	354836	133	0	0
T6	15655	0	0	0
T9	849199	0	0	0
T11	12415	0	0	0
T12	19430	0	0	0
T17	4113	0	0	0
T19	0	36	0	0
T20	0	24	0	0
T21	0	114	0	0
T30	61764	0	0	0
T37	18164	0	0	0
T55	17937	0	0	0
T74	14431	0	0	0
T227	0	106	0	0
T276	0	100	0	0
T337	0	37	0	0
T338	0	78	0	0
T339	0	38	0	0
T340	0	62	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468606785	3767	0	0
T5	354836	87	0	0
T6	15655	0	0	0
T9	849199	0	0	0
T11	12415	0	0	0
T12	19430	0	0	0
T17	4113	0	0	0
T19	0	67	0	0
T20	0	20	0	0
T21	0	151	0	0
T30	61764	0	0	0
T37	18164	0	0	0
T55	17937	0	0	0
T74	14431	0	0	0
T227	0	127	0	0
T276	0	110	0	0
T337	0	43	0	0
T338	0	125	0	0
T339	0	82	0	0
T340	0	47	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468606785	3500	0	0
T5	354836	94	0	0
T6	15655	0	0	0
T9	849199	0	0	0
T11	12415	0	0	0
T12	19430	0	0	0
T17	4113	0	0	0
T19	0	52	0	0
T20	0	22	0	0
T21	0	103	0	0
T30	61764	0	0	0
T37	18164	0	0	0
T55	17937	0	0	0
T74	14431	0	0	0
T227	0	113	0	0
T276	0	104	0	0
T337	0	53	0	0
T338	0	140	0	0
T339	0	49	0	0
T340	0	55	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468606785	3225	0	0
T5	354836	89	0	0
T6	15655	0	0	0
T9	849199	0	0	0
T11	12415	0	0	0
T12	19430	0	0	0
T17	4113	0	0	0
T19	0	51	0	0
T20	0	49	0	0
T21	0	141	0	0
T30	61764	0	0	0
T37	18164	0	0	0
T55	17937	0	0	0
T74	14431	0	0	0
T227	0	102	0	0
T276	0	111	0	0
T337	0	34	0	0
T338	0	118	0	0
T339	0	34	0	0
T340	0	43	0	0