Unified Coverage Report :: Module :: otp_ctrl_dai

Module : otp_ctrl_dai

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.07	94.33	90.59		83.33	87.10	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp_ctrl_dai	93.73	95.88	95.06		87.72	90.00	100.00

---

Module Instance : tb.dut.u_otp_ctrl_dai

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.73	95.88	95.06		87.72	90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.38	85.64	91.96	100.00	87.72	89.73	87.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.18		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_part_sel_idx	74.55	65.65	89.83			88.89	53.85
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : otp_ctrl_dai

	Line No.	Total	Covered	Percent
TOTAL		247	233	94.33
ALWAYS	169	3	3	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	179	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
ALWAYS	187	199	185	92.96
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
ALWAYS	753	11	11	100.00
CONT_ASSIGN	796	1	1	100.00
CONT_ASSIGN	797	1	1	100.00
ALWAYS	803	3	3	100.00
ALWAYS	806	14	14	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
169	1	1
170	1	1
172	1	1
			MISSING_ELSE
177	1	1
179	1	1
180	1	1
184	1	1
187	1	1
190	1	1
191	1	1
194	1	1
195	1	1
196	1	1
199	1	1
200	1	1
203	1	1
206	1	1
207	1	1
208	1	1
209	1	1
212	1	1
213	1	1
214	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
225	1	1
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
			==> MISSING_ELSE
			MISSING_ELSE
247	1	1
248	1	1
249	1	1
250	1	1
251	0	1
252	0	1
254	1	1
			MISSING_ELSE
263	1	1
264	1	1
265	1	1
266	1	1
267	1	1
			MISSING_ELSE
274	1	1
275	1	1
277	1	1
278	1	1
279	1	1
281	1	1
283	1	1
284	1	1
287	1	1
289	1	1
290	1	1
292	1	1
293	1	1
295	1	1
299	1	1
300	1	1
301	1	1
			MISSING_ELSE
313	1	1
317	1	1
320	1	1
321	1	1
323	1	1
325	1	1
326	1	1
			MISSING_ELSE
329	1	1
330	1	1
331	1	1
341	1	1
345	1	1
347	1	1
348	1	1
350	1	1
351	1	1
353	1	1
354	1	1
357	1	1
358	1	1
			MISSING_ELSE
361	1	1
362	1	1
			MISSING_ELSE
369	0	1
370	0	1
380	1	1
381	1	1
382	1	1
383	1	1
384	1	1
385	1	1
			MISSING_ELSE
393	1	1
394	1	1
395	1	1
396	1	1
397	1	1
398	1	1
399	1	1
			MISSING_ELSE
410	1	1
411	1	1
420	1	1
423	1	1
424	1	1
426	1	1
428	1	1
429	1	1
			MISSING_ELSE
433	1	1
434	1	1
435	1	1
436	1	1
444	1	1
446	1	1
456	1	1
458	1	1
459	0	1
460	0	1
463	1	1
464	1	1
465	1	1
467	1	1
468	1	1
			MISSING_ELSE
			MISSING_ELSE
476	0	1
477	0	1
487	1	1
489	1	1
495	1	1
496	1	1
497	1	1
498	1	1
499	1	1
			MISSING_ELSE
502	1	1
503	1	1
504	1	1
512	1	1
514	1	1
519	1	1
520	1	1
521	1	1
522	1	1
			MISSING_ELSE
528	0	1
529	0	1
536	1	1
537	1	1
539	1	1
540	1	1
541	1	1
			MISSING_ELSE
549	1	1
550	1	1
553	1	1
556	1	1
557	1	1
559	0	1
561	1	1
562	1	1
			MISSING_ELSE
565	1	1
566	1	1
567	1	1
577	1	1
578	1	1
579	1	1
581	1	1
582	0	1
583	0	1
585	1	1
586	1	1
588	1	1
589	0	1
			MISSING_ELSE
			MISSING_ELSE
600	1	1
601	1	1
603	1	1
605	1	1
606	1	1
607	1	1
608	1	1
			==> MISSING_ELSE
611	1	1
612	1	1
			MISSING_ELSE
616	1	1
617	1	1
			MISSING_ELSE
620	1	1
621	1	1
			MISSING_ELSE
630	1	1
631	1	1
632	1	1
633	1	1
634	1	1
			==> MISSING_ELSE
641	1	1
642	1	1
643	1	1
644	1	1
645	1	1
			MISSING_ELSE
656	1	1
657	1	1
658	1	1
659	1	1
660	1	1
			MISSING_ELSE
668	1	1
669	1	1
			MISSING_ELSE
684	1	1
685	1	1
686	1	1
687	1	1
688	1	1
			MISSING_ELSE
			MISSING_ELSE
718	1	1
721	10	10
753	1	1
754	1	1
757	1	1
758	1	1
759	1	1
761	1	1
762	1	1
763	1	1
765	1	1
768	1	1
769	1	1
			MISSING_ELSE
796	1	1
797	1	1
803	3	3
806	1	1
807	1	1
808	1	1
809	1	1
811	1	1
812	1	1
815	1	1
816	1	1
817	1	1
818	1	1
819	1	1
820	1	1
821	1	1
823	1	1
			MISSING_ELSE

---

Cond Coverage for Module : otp_ctrl_dai

	Total	Covered	Percent
Conditions	85	77	90.59
Logical	85	77	90.59
Non-Logical	0	0
Event	0	0

 LINE       170
 EXPRESSION (((!otp_ctrl_part_pkg::PartInfo[part_idx].integrity)) && (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))
             --------------------------1-------------------------    -----------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T74,T75

 LINE       184
 EXPRESSION ((state_q == IdleSt) ? data_q : '0)
             ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       184
 SUB-EXPRESSION (state_q == IdleSt)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       266
 EXPRESSION (part_init_done_i == {otp_ctrl_reg_pkg::NumPart {1'b1}})
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       350
 EXPRESSION (otp_ctrl_part_pkg::PartInfo[part_idx].secret && (otp_addr_o != digest_addr_lut[part_idx]))
             ----------------------1---------------------    --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T5,T6,T9
1	1	Covered	T1,T2,T8

 LINE       350
 SUB-EXPRESSION (otp_addr_o != digest_addr_lut[part_idx])
                --------------------1--------------------

-1-	Status	Tests
0	Covered	T5,T11,T6
1	Covered	T1,T2,T8

 LINE       357
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T4,T31,T115

 LINE       384
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T8

 LINE       467
 EXPRESSION (otp_err == MacroWriteBlankError)
            ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T9,T10,T183

 LINE       498
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T8

 LINE       540
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T5

 LINE       588
 EXPRESSION (otp_err == MacroEccCorrError)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Not Covered

 LINE       603
 EXPRESSION (otp_addr_o == digest_addr_lut[part_idx])
            --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T5,T11

 LINE       668
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T24,T25,T26

 LINE       687
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T1,T2,T8

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b00001000000) & ({1'b0, dai_addr_i} < gen_part_sel[1].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T7

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b00110110000) & ({1'b0, dai_addr_i} < gen_part_sel[2].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T7

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b10001111000) & ({1'b0, dai_addr_i} < gen_part_sel[3].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T7

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b11001010000) & ({1'b0, dai_addr_i} < gen_part_sel[4].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T7

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b11001111000) & ({1'b0, dai_addr_i} < gen_part_sel[5].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T7

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b11011000000) & ({1'b0, dai_addr_i} < gen_part_sel[6].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T7

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b11011010000) & ({1'b0, dai_addr_i} < gen_part_sel[7].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T8

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b11011111000) & ({1'b0, dai_addr_i} < gen_part_sel[8].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b11101010000) & ({1'b0, dai_addr_i} < gen_part_sel[9].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T10,T15
1	1	Covered	T1,T2,T7

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b11110101000) & ({1'b0, dai_addr_i} < gen_part_sel[10].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   --------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T10,T15

 LINE       761
 EXPRESSION (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (base_sel_q == PartOffset))
             -----------------------1-----------------------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T53
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T5

 LINE       761
 SUB-EXPRESSION (base_sel_q == PartOffset)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       765
 EXPRESSION 
 Number  Term
      1  (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest || otp_ctrl_part_pkg::PartInfo[part_idx].sw_digest) && 
      2  (base_sel_q == DaiOffset) && 
      3  ({dai_addr_i[(otp_ctrl_reg_pkg::OtpByteAddrWidth - 1):3], 2'b0} == digest_addr_lut[part_idx]))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T223,T224
1	0	1	Covered	T225,T226,T227
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T2,T5,T11

 LINE       765
 SUB-EXPRESSION (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest || otp_ctrl_part_pkg::PartInfo[part_idx].sw_digest)
                 -----------------------1-----------------------    -----------------------2-----------------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T15
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7

 LINE       765
 SUB-EXPRESSION (base_sel_q == DaiOffset)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T5,T53
1	Covered	T1,T2,T3

 LINE       765
 SUB-EXPRESSION ({dai_addr_i[(otp_ctrl_reg_pkg::OtpByteAddrWidth - 1):3], 2'b0} == digest_addr_lut[part_idx])
                ----------------------------------------------1----------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T11

 LINE       818
 EXPRESSION (data_sel == ScrmblData)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T1,T2,T8

 LINE       820
 EXPRESSION (data_sel == DaiData)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T1,T2,T8

---

FSM Coverage for Module : otp_ctrl_dai

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	48	42	87.50
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DescrSt	351	Covered	T1,T2,T8
DescrWaitSt	385	Covered	T1,T2,T8
DigClrSt	299	Covered	T1,T2,T5
DigFinSt	608	Covered	T1,T5,T11
DigPadSt	612	Covered	T1,T5,T55
DigReadSt	541	Covered	T1,T2,T5
DigReadWaitSt	562	Covered	T1,T2,T5
DigSt	586	Covered	T1,T2,T5
DigWaitSt	645	Covered	T1,T5,T11
ErrorSt	251	Covered	T1,T2,T8
IdleSt	267	Covered	T1,T2,T3
InitOtpSt	238	Covered	T1,T2,T3
InitPartSt	254	Covered	T1,T2,T3
ReadSt	281	Covered	T1,T2,T8
ReadWaitSt	326	Covered	T1,T2,T8
ResetSt	231	Covered	T1,T2,T3
ScrSt	293	Covered	T1,T2,T8
ScrWaitSt	499	Covered	T1,T2,T8
WriteSt	295	Covered	T1,T2,T8
WriteWaitSt	429	Covered	T1,T2,T8

transitions	Line No.	Covered	Tests
DescrSt->DescrWaitSt	385	Covered	T1,T2,T8
DescrSt->ErrorSt	685	Covered	T228
DescrWaitSt->ErrorSt	685	Covered	T8,T185,T229
DescrWaitSt->IdleSt	397	Covered	T1,T2,T7
DigClrSt->DigReadSt	541	Covered	T1,T2,T5
DigClrSt->ErrorSt	685	Not Covered
DigFinSt->DigWaitSt	645	Covered	T1,T5,T11
DigFinSt->ErrorSt	685	Covered	T230,T231,T232
DigPadSt->DigFinSt	634	Covered	T1,T5,T55
DigPadSt->ErrorSt	685	Not Covered
DigReadSt->DigReadWaitSt	562	Covered	T1,T2,T5
DigReadSt->ErrorSt	685	Covered	T233
DigReadSt->IdleSt	565	Covered	T5,T30,T9
DigReadWaitSt->DigSt	586	Covered	T1,T2,T5
DigReadWaitSt->ErrorSt	582	Covered	T2,T55,T73
DigSt->DigFinSt	608	Covered	T1,T5,T11
DigSt->DigPadSt	612	Covered	T1,T5,T55
DigSt->DigReadSt	621	Covered	T1,T2,T5
DigSt->ErrorSt	685	Covered	T234,T235,T236
DigWaitSt->ErrorSt	685	Covered	T237,T238,T239
DigWaitSt->WriteSt	659	Covered	T1,T5,T11
IdleSt->DigClrSt	299	Covered	T1,T2,T5
IdleSt->ErrorSt	685	Covered	T5,T12,T9
IdleSt->ReadSt	281	Covered	T1,T2,T8
IdleSt->ScrSt	293	Covered	T1,T2,T8
IdleSt->WriteSt	295	Covered	T1,T2,T7
InitOtpSt->ErrorSt	251	Covered	T83,T84,T85
InitOtpSt->InitPartSt	254	Covered	T1,T2,T3
InitPartSt->ErrorSt	685	Covered	T1,T7,T74
InitPartSt->IdleSt	267	Covered	T1,T2,T3
ReadSt->ErrorSt	685	Not Covered
ReadSt->IdleSt	329	Covered	T2,T5,T11
ReadSt->ReadWaitSt	326	Covered	T1,T2,T8
ReadWaitSt->DescrSt	351	Covered	T1,T2,T8
ReadWaitSt->ErrorSt	361	Covered	T4,T9,T10
ReadWaitSt->IdleSt	353	Covered	T1,T2,T7
ResetSt->ErrorSt	685	Covered	T148,T240,T142
ResetSt->InitOtpSt	238	Covered	T1,T2,T3
ScrSt->ErrorSt	685	Not Covered
ScrSt->IdleSt	502	Covered	T5,T11,T30
ScrSt->ScrWaitSt	499	Covered	T1,T2,T8
ScrWaitSt->ErrorSt	528	Not Covered
ScrWaitSt->WriteSt	521	Covered	T1,T2,T8
WriteSt->ErrorSt	685	Not Covered
WriteSt->IdleSt	434	Covered	T5,T6,T30
WriteSt->WriteWaitSt	429	Covered	T1,T2,T8
WriteWaitSt->ErrorSt	459	Covered	T241,T242,T169
WriteWaitSt->IdleSt	464	Covered	T1,T2,T8

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	12	8	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	330	Covered	T2,T5,T11
FsmStateError	370	Covered	T1,T2,T8
MacroEccCorrError	358	Covered	T4,T31,T115
NoError	172	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AccessError->FsmStateError	370	Covered	T5,T243,T14
AccessError->MacroEccCorrError	358	Not Covered
AccessError->NoError	172	Covered	T2,T5,T11
FsmStateError->AccessError	330	Not Covered
FsmStateError->MacroEccCorrError	358	Not Covered
FsmStateError->NoError	172	Covered	T1,T2,T8
MacroEccCorrError->AccessError	330	Not Covered
MacroEccCorrError->FsmStateError	370	Covered	T152,T214,T244
MacroEccCorrError->NoError	172	Covered	T4,T31,T115
NoError->AccessError	330	Covered	T2,T5,T11
NoError->FsmStateError	370	Covered	T1,T2,T8
NoError->MacroEccCorrError	358	Covered	T4,T31,T115

---

Branch Coverage for Module : otp_ctrl_dai

	Line No.	Total	Covered	Percent
Branches		93	81	87.10
TERNARY	184	2	2	100.00
IF	170	2	2	100.00
CASE	225	74	62	83.78
IF	684	3	3	100.00
IF	757	4	4	100.00
IF	803	2	2	100.00
IF	806	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	184	((state_q == IdleSt)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	170	if (((!otp_ctrl_part_pkg::PartInfo[part_idx].integrity) && (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError})))

Branches:

-1-	Status	Tests
1	Covered	T7,T74,T75
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	225	case (state_q)
-2-:	235	if (init_req_i)
-3-:	237	if (otp_gnt_i)
-4-:	249	if (otp_rvalid_i)
-5-:	250	if ((!(otp_err inside {NoError, MacroEccCorrError})))
-6-:	266	if ((part_init_done_i == {otp_ctrl_reg_pkg::NumPart {1'b1}}))
-7-:	275	if (dai_req_i)
-8-:	279	case (dai_cmd_i)
-9-:	292	if (otp_ctrl_part_pkg::PartInfo[part_idx].secret)
-10-:	313	if ((part_sel_valid && (prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].read_lock) || (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (otp_addr_o == digest_addr_lut[part_idx])))))
-11-:	320	if (otp_ctrl_part_pkg::PartInfo[part_idx].integrity)
-12-:	325	if (otp_gnt_i)
-13-:	341	if ((part_sel_valid && (prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].read_lock) || (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (otp_addr_o == digest_addr_lut[part_idx])))))
-14-:	345	if (otp_rvalid_i)
-15-:	347	if ((otp_err inside {NoError, MacroEccCorrError}))
-16-:	350	if ((otp_ctrl_part_pkg::PartInfo[part_idx].secret && (otp_addr_o != digest_addr_lut[part_idx])))
-17-:	357	if ((otp_err != NoError))
-18-:	384	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-19-:	396	if (scrmbl_valid_i)
-20-:	411	if (((part_sel_valid && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock)) && ((((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == PartOffset)) && (otp_addr_o == digest_addr_lut[part_idx])) || ((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx]))) || ((otp_ctrl_part_pkg::PartInfo[part_idx].variant != Buffered) && (base_sel_q == DaiOffset)))))
-21-:	423	if (otp_ctrl_part_pkg::PartInfo[part_idx].integrity)
-22-:	428	if (otp_gnt_i)
-23-:	446	if (((part_sel_valid && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock)) && ((((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == PartOffset)) && (otp_addr_o == digest_addr_lut[part_idx])) || ((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx]))) || ((otp_ctrl_part_pkg::PartInfo[part_idx].variant != Buffered) && (base_sel_q == DaiOffset)))))
-24-:	456	if (otp_rvalid_i)
-25-:	458	if ((!(otp_err inside {NoError, MacroWriteBlankError})))
-26-:	467	if ((otp_err == MacroWriteBlankError))
-27-:	489	if (((part_sel_valid && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock)) && (((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].secret) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx]))))
-28-:	498	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-29-:	514	if (((part_sel_valid && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock)) && (((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].secret) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx]))))
-30-:	520	if (scrmbl_valid_i)
-31-:	540	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-32-:	550	if (((part_sel_valid && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].read_lock)) && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock)))
-33-:	556	if (otp_ctrl_part_pkg::PartInfo[part_idx].integrity)
-34-:	561	if (otp_gnt_i)
-35-:	578	if (otp_rvalid_i)
-36-:	581	if ((!(otp_err inside {NoError, MacroEccCorrError})))
-37-:	588	if ((otp_err == MacroEccCorrError))
-38-:	603	if ((otp_addr_o == digest_addr_lut[part_idx]))
-39-:	605	if ((!cnt[0]))
-40-:	607	if (scrmbl_ready_i)
-41-:	611	if (scrmbl_ready_i)
-42-:	616	if ((!cnt[0]))
-43-:	620	if (scrmbl_ready_i)
-44-:	633	if (scrmbl_ready_i)
-45-:	644	if (scrmbl_ready_i)
-46-:	658	if (scrmbl_valid_i)
-47-:	668	if ((error_q == NoError))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	-31-	-32-	-33-	-34-	-35-	-36-	-37-	-38-	-39-	-40-	-41-	-42-	-43-	-44-	-45-	-46-	-47-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitOtpSt	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitOtpSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitOtpSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitPartSt	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitPartSt	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	DaiRead	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
IdleSt	-	-	-	-	-	1	DaiWrite	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
IdleSt	-	-	-	-	-	1	DaiWrite	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
IdleSt	-	-	-	-	-	1	DaiDigest	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
IdleSt	-	-	-	-	-	1	default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
ReadSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T5
ReadSt	-	-	-	-	-	-	-	-	1	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
ReadSt	-	-	-	-	-	-	-	-	1	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T10,T153
ReadSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T11
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	1	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	1	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T31,T115
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DescrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
DescrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T9,T10
DescrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
DescrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
WriteSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
WriteSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
WriteSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
WriteSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T10,T153
WriteSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T30
WriteWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
WriteWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T183
WriteWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
WriteWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
WriteWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
ScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T30,T9
ScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T11,T30
ScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
ScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
ScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
DigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T30,T9
DigReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
DigReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
DigReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T10,T153
DigReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T30,T9
DigReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	1	-	-	-	-	-	-	-	-	-	-	Not Covered
DigReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
DigReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	Covered	T1,T5,T11
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	Not Covered
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	1	-	-	-	-	-	-	Covered	T1,T5,T55
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	-	-	-	-	-	-	Covered	T98
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T5
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T5
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T5
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T5
DigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T1,T5,T55
DigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Not Covered
DigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T5,T11
DigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T5,T11
DigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T5,T11
DigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T5,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T24,T25,T26
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T25,T26

	LineNo.	Expression
-1-:	684	if ((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err))
-2-:	687	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T8
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	757	if (otp_ctrl_part_pkg::PartInfo[part_idx].secret)
-2-:	761	if ((otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (base_sel_q == PartOffset)))
-3-:	765	if ((((otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest || otp_ctrl_part_pkg::PartInfo[part_idx].sw_digest) && (base_sel_q == DaiOffset)) && ({dai_addr_i[(otp_ctrl_reg_pkg::OtpByteAddrWidth - 1):3], 2'b0} == digest_addr_lut[part_idx])))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T8
0	1	-	Covered	T1,T2,T5
0	0	1	Covered	T2,T5,T11
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	803	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	806	if ((!rst_ni))
-2-:	815	if (data_clr)
-3-:	817	if (data_en)
-4-:	818	if ((data_sel == ScrmblData))
-5-:	820	if ((data_sel == DaiData))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T2,T3
0	0	1	1	-	Covered	T1,T2,T8
0	0	1	0	1	Covered	T1,T2,T8
0	0	1	0	0	Covered	T1,T2,T8
0	0	0	-	-	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl_dai

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckNativeOtpWidth0_A	1155	1155	0	0
CheckNativeOtpWidth1_A	1155	1155	0	0
DaiIdleKnown_A	465884233	465042490	0	0
DaiRdataKnown_A	465884233	465042490	0	0
ErrorKnown_A	465884233	465042490	0	0
InitDoneKnown_A	465884233	465042490	0	0
OtpAddrKnown_A	465884233	465042490	0	0
OtpCmdKnown_A	465884233	465042490	0	0
OtpErrorState_A	465884233	388	0	0
OtpReqKnown_A	465884233	465042490	0	0
OtpSizeKnown_A	465884233	465042490	0	0
OtpWdataKnown_A	465884233	465042490	0	0
PartInitReqKnown_A	465884233	465042490	0	0
PartSelMustBeOnehot_A	465884233	465042490	0	0
ScrmblBlockWidthGe8_A	465884233	465042490	0	0
ScrmblCmdKnown_A	465884233	465042490	0	0
ScrmblDataKnown_A	465884233	465042490	0	0
ScrmblModeKnown_A	465884233	465042490	0	0
ScrmblMtxReqKnown_A	465884233	465042490	0	0
ScrmblSelKnown_A	465884233	465042490	0	0
ScrmblValidKnown_A	465884233	465042490	0	0
gen_part_sel[0].PartEndMax_A	1155	1155	0	0
gen_part_sel[10].PartEndMax_A	1155	1155	0	0
gen_part_sel[1].PartEndMax_A	1155	1155	0	0
gen_part_sel[2].PartEndMax_A	1155	1155	0	0
gen_part_sel[3].PartEndMax_A	1155	1155	0	0
gen_part_sel[4].PartEndMax_A	1155	1155	0	0
gen_part_sel[5].PartEndMax_A	1155	1155	0	0
gen_part_sel[6].PartEndMax_A	1155	1155	0	0
gen_part_sel[7].PartEndMax_A	1155	1155	0	0
gen_part_sel[8].PartEndMax_A	1155	1155	0	0
gen_part_sel[9].PartEndMax_A	1155	1155	0	0
u_state_regs_A	465884233	465042490	0	0

CheckNativeOtpWidth0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

CheckNativeOtpWidth1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

DaiIdleKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

DaiRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	388	0	0
T4	17570	2	0	0
T5	354836	0	0	0
T6	15655	0	0	0
T9	0	3	0	0
T10	0	2	0	0
T11	12415	0	0	0
T12	19430	0	0	0
T15	0	1	0	0
T17	4113	0	0	0
T30	61764	0	0	0
T37	18164	0	0	0
T55	17937	0	0	0
T74	14431	0	0	0
T101	0	1	0	0
T116	0	6	0	0
T129	0	1	0	0
T141	0	6	0	0
T183	0	1	0	0
T245	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

PartInitReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

PartSelMustBeOnehot_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

ScrmblBlockWidthGe8_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

ScrmblCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

ScrmblDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

ScrmblModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

ScrmblMtxReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

ScrmblSelKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

ScrmblValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

gen_part_sel[0].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

gen_part_sel[10].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

gen_part_sel[1].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

gen_part_sel[2].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

gen_part_sel[3].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

gen_part_sel[4].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

gen_part_sel[5].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

gen_part_sel[6].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

gen_part_sel[7].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

gen_part_sel[8].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

gen_part_sel[9].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

Line Coverage for Instance : tb.dut.u_otp_ctrl_dai

	Line No.	Total	Covered	Percent
TOTAL		243	233	95.88
ALWAYS	169	3	3	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	179	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
ALWAYS	187	195	185	94.87
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
ALWAYS	753	11	11	100.00
CONT_ASSIGN	796	1	1	100.00
CONT_ASSIGN	797	1	1	100.00
ALWAYS	803	3	3	100.00
ALWAYS	806	14	14	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
169	1	1
170	1	1
172	1	1
			MISSING_ELSE
177	1	1
179	1	1
180	1	1
184	1	1
187	1	1
190	1	1
191	1	1
194	1	1
195	1	1
196	1	1
199	1	1
200	1	1
203	1	1
206	1	1
207	1	1
208	1	1
209	1	1
212	1	1
213	1	1
214	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
225	1	1
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
			==> MISSING_ELSE
			MISSING_ELSE
247	1	1
248	1	1
249	1	1
250	1	1
251		excluded
			Exclude Annotation: VC_COV_UNR
252		excluded
			Exclude Annotation: VC_COV_UNR
254	1	1
			MISSING_ELSE
263	1	1
264	1	1
265	1	1
266	1	1
267	1	1
			MISSING_ELSE
274	1	1
275	1	1
277	1	1
278	1	1
279	1	1
281	1	1
283	1	1
284	1	1
287	1	1
289	1	1
290	1	1
292	1	1
293	1	1
295	1	1
299	1	1
300	1	1
301	1	1
			MISSING_ELSE
313	1	1
317	1	1
320	1	1
321	1	1
323	1	1
325	1	1
326	1	1
			MISSING_ELSE
329	1	1
330	1	1
331	1	1
341	1	1
345	1	1
347	1	1
348	1	1
350	1	1
351	1	1
353	1	1
354	1	1
357	1	1
358	1	1
			MISSING_ELSE
361	1	1
362	1	1
			MISSING_ELSE
369	0	1
370	0	1
380	1	1
381	1	1
382	1	1
383	1	1
384	1	1
385	1	1
			MISSING_ELSE
393	1	1
394	1	1
395	1	1
396	1	1
397	1	1
398	1	1
399	1	1
			MISSING_ELSE
410	1	1
411	1	1
420	1	1
423	1	1
424	1	1
426	1	1
428	1	1
429	1	1
			MISSING_ELSE
433	1	1
434	1	1
435	1	1
436	1	1
444	1	1
446	1	1
456	1	1
458	1	1
459		excluded
			Exclude Annotation: VC_COV_UNR
460		excluded
			Exclude Annotation: VC_COV_UNR
463	1	1
464	1	1
465	1	1
467	1	1
468	1	1
			MISSING_ELSE
			MISSING_ELSE
476	0	1
477	0	1
487	1	1
489	1	1
495	1	1
496	1	1
497	1	1
498	1	1
499	1	1
			MISSING_ELSE
502	1	1
503	1	1
504	1	1
512	1	1
514	1	1
519	1	1
520	1	1
521	1	1
522	1	1
			MISSING_ELSE
528	0	1
529	0	1
536	1	1
537	1	1
539	1	1
540	1	1
541	1	1
			MISSING_ELSE
549	1	1
550	1	1
553	1	1
556	1	1
557	1	1
559	0	1
561	1	1
562	1	1
			MISSING_ELSE
565	1	1
566	1	1
567	1	1
577	1	1
578	1	1
579	1	1
581	1	1
582	0	1
583	0	1
585	1	1
586	1	1
588	1	1
589	0	1
			MISSING_ELSE
			MISSING_ELSE
600	1	1
601	1	1
603	1	1
605	1	1
606	1	1
607	1	1
608	1	1
			==> MISSING_ELSE
611	1	1
612	1	1
			MISSING_ELSE
616	1	1
617	1	1
			MISSING_ELSE
620	1	1
621	1	1
			MISSING_ELSE
630	1	1
631	1	1
632	1	1
633	1	1
634	1	1
			==> MISSING_ELSE
641	1	1
642	1	1
643	1	1
644	1	1
645	1	1
			MISSING_ELSE
656	1	1
657	1	1
658	1	1
659	1	1
660	1	1
			MISSING_ELSE
668	1	1
669	1	1
			MISSING_ELSE
684	1	1
685	1	1
686	1	1
687	1	1
688	1	1
			MISSING_ELSE
			MISSING_ELSE
718	1	1
721	10	10
753	1	1
754	1	1
757	1	1
758	1	1
759	1	1
761	1	1
762	1	1
763	1	1
765	1	1
768	1	1
769	1	1
			MISSING_ELSE
796	1	1
797	1	1
803	3	3
806	1	1
807	1	1
808	1	1
809	1	1
811	1	1
812	1	1
815	1	1
816	1	1
817	1	1
818	1	1
819	1	1
820	1	1
821	1	1
823	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_otp_ctrl_dai

	Total	Covered	Percent
Conditions	81	77	95.06
Logical	81	77	95.06
Non-Logical	0	0
Event	0	0

 LINE       170
 EXPRESSION (((!otp_ctrl_part_pkg::PartInfo[part_idx].integrity)) && (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))
             --------------------------1-------------------------    -----------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T74,T75

 LINE       184
 EXPRESSION ((state_q == IdleSt) ? data_q : '0)
             ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       184
 SUB-EXPRESSION (state_q == IdleSt)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       266
 EXPRESSION (part_init_done_i == {otp_ctrl_reg_pkg::NumPart {1'b1}})
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       350
 EXPRESSION (otp_ctrl_part_pkg::PartInfo[part_idx].secret && (otp_addr_o != digest_addr_lut[part_idx]))
             ----------------------1---------------------    --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T5,T6,T9
1	1	Covered	T1,T2,T8

 LINE       350
 SUB-EXPRESSION (otp_addr_o != digest_addr_lut[part_idx])
                --------------------1--------------------

-1-	Status	Tests
0	Covered	T5,T11,T6
1	Covered	T1,T2,T8

 LINE       357
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T4,T31,T115

 LINE       384
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Not Covered
1	1	Covered	T1,T2,T8

 LINE       467
 EXPRESSION (otp_err == MacroWriteBlankError)
            ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T9,T10,T183

 LINE       498
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Not Covered
1	1	Covered	T1,T2,T8

 LINE       540
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Not Covered
1	1	Covered	T1,T2,T5

 LINE       588
 EXPRESSION (otp_err == MacroEccCorrError)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Not Covered

 LINE       603
 EXPRESSION (otp_addr_o == digest_addr_lut[part_idx])
            --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T5,T11

 LINE       668
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T24,T25,T26

 LINE       687
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T1,T2,T8

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b00001000000) & ({1'b0, dai_addr_i} < gen_part_sel[1].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T7

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b00110110000) & ({1'b0, dai_addr_i} < gen_part_sel[2].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T7

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b10001111000) & ({1'b0, dai_addr_i} < gen_part_sel[3].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T7

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b11001010000) & ({1'b0, dai_addr_i} < gen_part_sel[4].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T7

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b11001111000) & ({1'b0, dai_addr_i} < gen_part_sel[5].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T7

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b11011000000) & ({1'b0, dai_addr_i} < gen_part_sel[6].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T7

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b11011010000) & ({1'b0, dai_addr_i} < gen_part_sel[7].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T8

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b11011111000) & ({1'b0, dai_addr_i} < gen_part_sel[8].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b11101010000) & ({1'b0, dai_addr_i} < gen_part_sel[9].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T10,T15
1	1	Covered	T1,T2,T7

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b11110101000) & ({1'b0, dai_addr_i} < gen_part_sel[10].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   --------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		vcs_gen_start:k=10:vcs_gen_end:VC_COV_UNR
1	1	Covered	T9,T10,T15

 LINE       761
 EXPRESSION (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (base_sel_q == PartOffset))
             -----------------------1-----------------------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T53
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T5

 LINE       761
 SUB-EXPRESSION (base_sel_q == PartOffset)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       765
 EXPRESSION 
 Number  Term
      1  (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest || otp_ctrl_part_pkg::PartInfo[part_idx].sw_digest) && 
      2  (base_sel_q == DaiOffset) && 
      3  ({dai_addr_i[(otp_ctrl_reg_pkg::OtpByteAddrWidth - 1):3], 2'b0} == digest_addr_lut[part_idx]))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T223,T224
1	0	1	Covered	T225,T226,T227
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T2,T5,T11

 LINE       765
 SUB-EXPRESSION (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest || otp_ctrl_part_pkg::PartInfo[part_idx].sw_digest)
                 -----------------------1-----------------------    -----------------------2-----------------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T15
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7

 LINE       765
 SUB-EXPRESSION (base_sel_q == DaiOffset)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T5,T53
1	Covered	T1,T2,T3

 LINE       765
 SUB-EXPRESSION ({dai_addr_i[(otp_ctrl_reg_pkg::OtpByteAddrWidth - 1):3], 2'b0} == digest_addr_lut[part_idx])
                ----------------------------------------------1----------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T11

 LINE       818
 EXPRESSION (data_sel == ScrmblData)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T1,T2,T8

 LINE       820
 EXPRESSION (data_sel == DaiData)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T1,T2,T8

---

FSM Coverage for Instance : tb.dut.u_otp_ctrl_dai

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	48	42	87.50
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DescrSt	351	Covered	T1,T2,T8
DescrWaitSt	385	Covered	T1,T2,T8
DigClrSt	299	Covered	T1,T2,T5
DigFinSt	608	Covered	T1,T5,T11
DigPadSt	612	Covered	T1,T5,T55
DigReadSt	541	Covered	T1,T2,T5
DigReadWaitSt	562	Covered	T1,T2,T5
DigSt	586	Covered	T1,T2,T5
DigWaitSt	645	Covered	T1,T5,T11
ErrorSt	251	Covered	T1,T2,T8
IdleSt	267	Covered	T1,T2,T3
InitOtpSt	238	Covered	T1,T2,T3
InitPartSt	254	Covered	T1,T2,T3
ReadSt	281	Covered	T1,T2,T8
ReadWaitSt	326	Covered	T1,T2,T8
ResetSt	231	Covered	T1,T2,T3
ScrSt	293	Covered	T1,T2,T8
ScrWaitSt	499	Covered	T1,T2,T8
WriteSt	295	Covered	T1,T2,T8
WriteWaitSt	429	Covered	T1,T2,T8

transitions	Line No.	Covered	Tests
DescrSt->DescrWaitSt	385	Covered	T1,T2,T8
DescrSt->ErrorSt	685	Covered	T228
DescrWaitSt->ErrorSt	685	Covered	T8,T185,T229
DescrWaitSt->IdleSt	397	Covered	T1,T2,T7
DigClrSt->DigReadSt	541	Covered	T1,T2,T5
DigClrSt->ErrorSt	685	Not Covered
DigFinSt->DigWaitSt	645	Covered	T1,T5,T11
DigFinSt->ErrorSt	685	Covered	T230,T231,T232
DigPadSt->DigFinSt	634	Covered	T1,T5,T55
DigPadSt->ErrorSt	685	Not Covered
DigReadSt->DigReadWaitSt	562	Covered	T1,T2,T5
DigReadSt->ErrorSt	685	Covered	T233
DigReadSt->IdleSt	565	Covered	T5,T30,T9
DigReadWaitSt->DigSt	586	Covered	T1,T2,T5
DigReadWaitSt->ErrorSt	582	Covered	T2,T55,T73
DigSt->DigFinSt	608	Covered	T1,T5,T11
DigSt->DigPadSt	612	Covered	T1,T5,T55
DigSt->DigReadSt	621	Covered	T1,T2,T5
DigSt->ErrorSt	685	Covered	T234,T235,T236
DigWaitSt->ErrorSt	685	Covered	T237,T238,T239
DigWaitSt->WriteSt	659	Covered	T1,T5,T11
IdleSt->DigClrSt	299	Covered	T1,T2,T5
IdleSt->ErrorSt	685	Covered	T5,T12,T9
IdleSt->ReadSt	281	Covered	T1,T2,T8
IdleSt->ScrSt	293	Covered	T1,T2,T8
IdleSt->WriteSt	295	Covered	T1,T2,T7
InitOtpSt->ErrorSt	251	Covered	T83,T84,T85
InitOtpSt->InitPartSt	254	Covered	T1,T2,T3
InitPartSt->ErrorSt	685	Covered	T1,T7,T74
InitPartSt->IdleSt	267	Covered	T1,T2,T3
ReadSt->ErrorSt	685	Not Covered
ReadSt->IdleSt	329	Covered	T2,T5,T11
ReadSt->ReadWaitSt	326	Covered	T1,T2,T8
ReadWaitSt->DescrSt	351	Covered	T1,T2,T8
ReadWaitSt->ErrorSt	361	Covered	T4,T9,T10
ReadWaitSt->IdleSt	353	Covered	T1,T2,T7
ResetSt->ErrorSt	685	Covered	T148,T240,T142
ResetSt->InitOtpSt	238	Covered	T1,T2,T3
ScrSt->ErrorSt	685	Not Covered
ScrSt->IdleSt	502	Covered	T5,T11,T30
ScrSt->ScrWaitSt	499	Covered	T1,T2,T8
ScrWaitSt->ErrorSt	528	Not Covered
ScrWaitSt->WriteSt	521	Covered	T1,T2,T8
WriteSt->ErrorSt	685	Not Covered
WriteSt->IdleSt	434	Covered	T5,T6,T30
WriteSt->WriteWaitSt	429	Covered	T1,T2,T8
WriteWaitSt->ErrorSt	459	Covered	T241,T242,T169
WriteWaitSt->IdleSt	464	Covered	T1,T2,T8

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	9	8	88.89
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	330	Covered	T2,T5,T11
FsmStateError	370	Covered	T1,T2,T8
MacroEccCorrError	358	Covered	T4,T31,T115
NoError	172	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->FsmStateError	370	Covered	T5,T243,T14
AccessError->MacroEccCorrError	358	Excluded		VC_COV_UNR
AccessError->NoError	172	Covered	T2,T5,T11
FsmStateError->AccessError	330	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	358	Excluded		VC_COV_UNR
FsmStateError->NoError	172	Covered	T1,T2,T8
MacroEccCorrError->AccessError	330	Not Covered
MacroEccCorrError->FsmStateError	370	Covered	T152,T214,T244
MacroEccCorrError->NoError	172	Covered	T4,T31,T115
NoError->AccessError	330	Covered	T2,T5,T11
NoError->FsmStateError	370	Covered	T1,T2,T8
NoError->MacroEccCorrError	358	Covered	T4,T31,T115

---

Branch Coverage for Instance : tb.dut.u_otp_ctrl_dai

	Line No.	Total	Covered	Percent
Branches		90	81	90.00
TERNARY	184	2	2	100.00
IF	170	2	2	100.00
CASE	225	71	62	87.32
IF	684	3	3	100.00
IF	757	4	4	100.00
IF	803	2	2	100.00
IF	806	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	184	((state_q == IdleSt)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	170	if (((!otp_ctrl_part_pkg::PartInfo[part_idx].integrity) && (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError})))

Branches:

-1-	Status	Tests
1	Covered	T7,T74,T75
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	225	case (state_q)
-2-:	235	if (init_req_i)
-3-:	237	if (otp_gnt_i)
-4-:	249	if (otp_rvalid_i)
-5-:	250	if ((!(otp_err inside {NoError, MacroEccCorrError})))
-6-:	266	if ((part_init_done_i == {otp_ctrl_reg_pkg::NumPart {1'b1}}))
-7-:	275	if (dai_req_i)
-8-:	279	case (dai_cmd_i)
-9-:	292	if (otp_ctrl_part_pkg::PartInfo[part_idx].secret)
-10-:	313	if ((part_sel_valid && (prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].read_lock) || (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (otp_addr_o == digest_addr_lut[part_idx])))))
-11-:	320	if (otp_ctrl_part_pkg::PartInfo[part_idx].integrity)
-12-:	325	if (otp_gnt_i)
-13-:	341	if ((part_sel_valid && (prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].read_lock) || (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (otp_addr_o == digest_addr_lut[part_idx])))))
-14-:	345	if (otp_rvalid_i)
-15-:	347	if ((otp_err inside {NoError, MacroEccCorrError}))
-16-:	350	if ((otp_ctrl_part_pkg::PartInfo[part_idx].secret && (otp_addr_o != digest_addr_lut[part_idx])))
-17-:	357	if ((otp_err != NoError))
-18-:	384	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-19-:	396	if (scrmbl_valid_i)
-20-:	411	if (((part_sel_valid && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock)) && ((((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == PartOffset)) && (otp_addr_o == digest_addr_lut[part_idx])) || ((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx]))) || ((otp_ctrl_part_pkg::PartInfo[part_idx].variant != Buffered) && (base_sel_q == DaiOffset)))))
-21-:	423	if (otp_ctrl_part_pkg::PartInfo[part_idx].integrity)
-22-:	428	if (otp_gnt_i)
-23-:	446	if (((part_sel_valid && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock)) && ((((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == PartOffset)) && (otp_addr_o == digest_addr_lut[part_idx])) || ((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx]))) || ((otp_ctrl_part_pkg::PartInfo[part_idx].variant != Buffered) && (base_sel_q == DaiOffset)))))
-24-:	456	if (otp_rvalid_i)
-25-:	458	if ((!(otp_err inside {NoError, MacroWriteBlankError})))
-26-:	467	if ((otp_err == MacroWriteBlankError))
-27-:	489	if (((part_sel_valid && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock)) && (((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].secret) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx]))))
-28-:	498	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-29-:	514	if (((part_sel_valid && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock)) && (((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].secret) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx]))))
-30-:	520	if (scrmbl_valid_i)
-31-:	540	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-32-:	550	if (((part_sel_valid && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].read_lock)) && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock)))
-33-:	556	if (otp_ctrl_part_pkg::PartInfo[part_idx].integrity)
-34-:	561	if (otp_gnt_i)
-35-:	578	if (otp_rvalid_i)
-36-:	581	if ((!(otp_err inside {NoError, MacroEccCorrError})))
-37-:	588	if ((otp_err == MacroEccCorrError))
-38-:	603	if ((otp_addr_o == digest_addr_lut[part_idx]))
-39-:	605	if ((!cnt[0]))
-40-:	607	if (scrmbl_ready_i)
-41-:	611	if (scrmbl_ready_i)
-42-:	616	if ((!cnt[0]))
-43-:	620	if (scrmbl_ready_i)
-44-:	633	if (scrmbl_ready_i)
-45-:	644	if (scrmbl_ready_i)
-46-:	658	if (scrmbl_valid_i)
-47-:	668	if ((error_q == NoError))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	-31-	-32-	-33-	-34-	-35-	-36-	-37-	-38-	-39-	-40-	-41-	-42-	-43-	-44-	-45-	-46-	-47-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitOtpSt	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitOtpSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitOtpSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitPartSt	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitPartSt	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	DaiRead	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
IdleSt	-	-	-	-	-	1	DaiWrite	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
IdleSt	-	-	-	-	-	1	DaiWrite	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
IdleSt	-	-	-	-	-	1	DaiDigest	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
IdleSt	-	-	-	-	-	1	default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
ReadSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T5
ReadSt	-	-	-	-	-	-	-	-	1	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
ReadSt	-	-	-	-	-	-	-	-	1	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T10,T153
ReadSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T11
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	1	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	1	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T31,T115
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DescrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
DescrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T9,T10
DescrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
DescrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
WriteSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
WriteSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
WriteSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
WriteSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T10,T153
WriteSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T30
WriteWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
WriteWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T183
WriteWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
WriteWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
WriteWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
ScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T30,T9
ScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T11,T30
ScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
ScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
ScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
DigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T30,T9
DigReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
DigReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
DigReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T10,T153
DigReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T30,T9
DigReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	1	-	-	-	-	-	-	-	-	-	-	Not Covered
DigReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
DigReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	Covered	T1,T5,T11
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	Not Covered
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	1	-	-	-	-	-	-	Covered	T1,T5,T55
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	-	-	-	-	-	-	Covered	T98
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T5
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T5
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T5
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T5
DigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T1,T5,T55
DigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Not Covered
DigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T5,T11
DigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T5,T11
DigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T5,T11
DigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T5,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T24,T25,T26
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T25,T26

	LineNo.	Expression
-1-:	684	if ((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err))
-2-:	687	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T8
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	757	if (otp_ctrl_part_pkg::PartInfo[part_idx].secret)
-2-:	761	if ((otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (base_sel_q == PartOffset)))
-3-:	765	if ((((otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest || otp_ctrl_part_pkg::PartInfo[part_idx].sw_digest) && (base_sel_q == DaiOffset)) && ({dai_addr_i[(otp_ctrl_reg_pkg::OtpByteAddrWidth - 1):3], 2'b0} == digest_addr_lut[part_idx])))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T8
0	1	-	Covered	T1,T2,T5
0	0	1	Covered	T2,T5,T11
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	803	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	806	if ((!rst_ni))
-2-:	815	if (data_clr)
-3-:	817	if (data_en)
-4-:	818	if ((data_sel == ScrmblData))
-5-:	820	if ((data_sel == DaiData))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T2,T3
0	0	1	1	-	Covered	T1,T2,T8
0	0	1	0	1	Covered	T1,T2,T8
0	0	1	0	0	Covered	T1,T2,T8
0	0	0	-	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_otp_ctrl_dai

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckNativeOtpWidth0_A	1155	1155	0	0
CheckNativeOtpWidth1_A	1155	1155	0	0
DaiIdleKnown_A	465884233	465042490	0	0
DaiRdataKnown_A	465884233	465042490	0	0
ErrorKnown_A	465884233	465042490	0	0
InitDoneKnown_A	465884233	465042490	0	0
OtpAddrKnown_A	465884233	465042490	0	0
OtpCmdKnown_A	465884233	465042490	0	0
OtpErrorState_A	465884233	388	0	0
OtpReqKnown_A	465884233	465042490	0	0
OtpSizeKnown_A	465884233	465042490	0	0
OtpWdataKnown_A	465884233	465042490	0	0
PartInitReqKnown_A	465884233	465042490	0	0
PartSelMustBeOnehot_A	465884233	465042490	0	0
ScrmblBlockWidthGe8_A	465884233	465042490	0	0
ScrmblCmdKnown_A	465884233	465042490	0	0
ScrmblDataKnown_A	465884233	465042490	0	0
ScrmblModeKnown_A	465884233	465042490	0	0
ScrmblMtxReqKnown_A	465884233	465042490	0	0
ScrmblSelKnown_A	465884233	465042490	0	0
ScrmblValidKnown_A	465884233	465042490	0	0
gen_part_sel[0].PartEndMax_A	1155	1155	0	0
gen_part_sel[10].PartEndMax_A	1155	1155	0	0
gen_part_sel[1].PartEndMax_A	1155	1155	0	0
gen_part_sel[2].PartEndMax_A	1155	1155	0	0
gen_part_sel[3].PartEndMax_A	1155	1155	0	0
gen_part_sel[4].PartEndMax_A	1155	1155	0	0
gen_part_sel[5].PartEndMax_A	1155	1155	0	0
gen_part_sel[6].PartEndMax_A	1155	1155	0	0
gen_part_sel[7].PartEndMax_A	1155	1155	0	0
gen_part_sel[8].PartEndMax_A	1155	1155	0	0
gen_part_sel[9].PartEndMax_A	1155	1155	0	0
u_state_regs_A	465884233	465042490	0	0

CheckNativeOtpWidth0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

CheckNativeOtpWidth1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

DaiIdleKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

DaiRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	388	0	0
T4	17570	2	0	0
T5	354836	0	0	0
T6	15655	0	0	0
T9	0	3	0	0
T10	0	2	0	0
T11	12415	0	0	0
T12	19430	0	0	0
T15	0	1	0	0
T17	4113	0	0	0
T30	61764	0	0	0
T37	18164	0	0	0
T55	17937	0	0	0
T74	14431	0	0	0
T101	0	1	0	0
T116	0	6	0	0
T129	0	1	0	0
T141	0	6	0	0
T183	0	1	0	0
T245	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

PartInitReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

PartSelMustBeOnehot_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

ScrmblBlockWidthGe8_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

ScrmblCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

ScrmblDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

ScrmblModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

ScrmblMtxReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

ScrmblSelKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

ScrmblValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0

gen_part_sel[0].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

gen_part_sel[10].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

gen_part_sel[1].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

gen_part_sel[2].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

gen_part_sel[3].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

gen_part_sel[4].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

gen_part_sel[5].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

gen_part_sel[6].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

gen_part_sel[7].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

gen_part_sel[8].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

gen_part_sel[9].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465884233	465042490	0	0
T1	11776	11502	0	0
T2	16617	16426	0	0
T3	7967	7907	0	0
T4	17570	17246	0	0
T5	354836	354822	0	0
T6	15655	15247	0	0
T7	11718	11450	0	0
T8	15060	14797	0	0
T11	12415	11789	0	0
T12	19430	19138	0	0