Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

22596396

1

T1

3142

T2

378

T3

3968

full_word

7567758

1

T1

2360

T2

143

T3

2642

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30163874	1			T1	5502		T2	521		T3	6610
auto[TlIntgErrCmd]	96	1			T258	9		T259	3		T260	4
auto[TlIntgErrData]	100	1			T258	6		T259	6		T260	4
auto[TlIntgErrBoth]	84	1			T258	5		T259	1		T260	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9233564

1

T1

4858

T2

347

T3

5904

auto[1]

20930590

1

T1

644

T2

174

T3

706

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5843831	1			T1	2773		T2	281		T3	3522
auto[TlIntgErrNone]	partial	auto[1]	16752308	1			T1	369		T2	97		T3	446
auto[TlIntgErrNone]	full_word	auto[0]	3389590	1			T1	2085		T2	66		T3	2382
auto[TlIntgErrNone]	full_word	auto[1]	4178145	1			T1	275		T2	77		T3	260
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T258	3		T259	3		T260	1
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T258	4		T260	2		T344	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T260	1		T347	1		T342	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T258	2		T348	1		-	-
auto[TlIntgErrData]	partial	auto[0]	53	1			T258	2		T259	3		T260	3
auto[TlIntgErrData]	partial	auto[1]	39	1			T258	3		T259	3		T260	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T346	1		T347	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1			T258	1		T343	2		T348	2
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T258	2		T259	1		T260	2
auto[TlIntgErrBoth]	partial	auto[1]	35	1			T258	3		T344	2		T341	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T343	1		T347	1		T342	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T347	1		T349	1		-	-