Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.20	94.16	96.15	97.06		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	441918716	7070470	0	0
check_regwen_rd_A	441918716	3899	0	0
check_timeout_rd_A	441918716	2657	0	0
check_trigger_regwen_rd_A	441918716	3947	0	0
consistency_check_period_rd_A	441918716	4226	0	0
creator_sw_cfg_read_lock_rd_A	441918716	2684	0	0
direct_access_address_rd_A	441918716	2310	0	0
direct_access_wdata_0_rd_A	441918716	1313	0	0
direct_access_wdata_1_rd_A	441918716	1737	0	0
integrity_check_period_rd_A	441918716	4221	0	0
intr_enable_rd_A	441918716	4880	0	0
owner_sw_cfg_read_lock_rd_A	441918716	2375	0	0
rot_creator_auth_codesign_read_lock_rd_A	441918716	2683	0	0
rot_creator_auth_state_read_lock_rd_A	441918716	2633	0	0
vendor_test_read_lock_rd_A	441918716	2324	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441918716	7070470	0	0
T6	108362	127583	0	0
T13	0	67774	0	0
T14	0	47923	0	0
T15	0	204655	0	0
T17	0	53313	0	0
T18	0	108235	0	0
T28	50485	0	0	0
T51	55210	0	0	0
T54	17180	0	0	0
T67	148425	0	0	0
T91	21835	0	0	0
T101	19745	0	0	0
T136	89973	0	0	0
T172	11206	0	0	0
T173	22170	0	0	0
T202	0	87970	0	0
T223	0	27218	0	0
T266	0	25971	0	0
T267	0	94825	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441918716	3899	0	0
T6	108362	158	0	0
T14	0	16	0	0
T28	50485	0	0	0
T37	0	180	0	0
T51	55210	0	0	0
T54	17180	0	0	0
T67	148425	0	0	0
T91	21835	0	0	0
T101	19745	0	0	0
T136	89973	0	0	0
T172	11206	0	0	0
T173	22170	0	0	0
T202	0	101	0	0
T223	0	34	0	0
T234	0	30	0	0
T267	0	164	0	0
T312	0	106	0	0
T319	0	111	0	0
T320	0	59	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441918716	2657	0	0
T6	108362	156	0	0
T14	0	28	0	0
T28	50485	0	0	0
T37	0	245	0	0
T51	55210	0	0	0
T54	17180	0	0	0
T67	148425	0	0	0
T91	21835	0	0	0
T101	19745	0	0	0
T136	89973	0	0	0
T172	11206	0	0	0
T173	22170	0	0	0
T202	0	111	0	0
T223	0	26	0	0
T234	0	47	0	0
T267	0	145	0	0
T312	0	155	0	0
T319	0	111	0	0
T320	0	63	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441918716	3947	0	0
T6	108362	130	0	0
T14	0	23	0	0
T28	50485	0	0	0
T37	0	164	0	0
T51	55210	0	0	0
T54	17180	0	0	0
T67	148425	0	0	0
T91	21835	0	0	0
T101	19745	0	0	0
T136	89973	0	0	0
T172	11206	0	0	0
T173	22170	0	0	0
T202	0	116	0	0
T223	0	50	0	0
T234	0	54	0	0
T267	0	112	0	0
T312	0	120	0	0
T319	0	83	0	0
T320	0	60	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441918716	4226	0	0
T6	108362	157	0	0
T14	0	58	0	0
T28	50485	0	0	0
T37	0	218	0	0
T51	55210	0	0	0
T54	17180	0	0	0
T67	148425	0	0	0
T91	21835	0	0	0
T101	19745	0	0	0
T136	89973	0	0	0
T172	11206	0	0	0
T173	22170	0	0	0
T202	0	145	0	0
T223	0	38	0	0
T234	0	49	0	0
T267	0	131	0	0
T312	0	147	0	0
T319	0	107	0	0
T320	0	52	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441918716	2684	0	0
T6	108362	162	0	0
T14	0	48	0	0
T28	50485	0	0	0
T37	0	180	0	0
T51	55210	0	0	0
T54	17180	0	0	0
T67	148425	0	0	0
T91	21835	0	0	0
T101	19745	0	0	0
T136	89973	0	0	0
T172	11206	0	0	0
T173	22170	0	0	0
T202	0	90	0	0
T223	0	46	0	0
T234	0	46	0	0
T267	0	138	0	0
T312	0	179	0	0
T319	0	101	0	0
T320	0	71	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441918716	2310	0	0
T6	108362	177	0	0
T14	0	45	0	0
T28	50485	0	0	0
T37	0	194	0	0
T51	55210	0	0	0
T54	17180	0	0	0
T67	148425	0	0	0
T91	21835	0	0	0
T101	19745	0	0	0
T136	89973	0	0	0
T172	11206	0	0	0
T173	22170	0	0	0
T202	0	128	0	0
T223	0	63	0	0
T234	0	67	0	0
T267	0	112	0	0
T312	0	122	0	0
T319	0	127	0	0
T320	0	46	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441918716	1313	0	0
T6	108362	110	0	0
T14	0	31	0	0
T28	50485	0	0	0
T37	0	113	0	0
T51	55210	0	0	0
T54	17180	0	0	0
T67	148425	0	0	0
T91	21835	0	0	0
T101	19745	0	0	0
T136	89973	0	0	0
T172	11206	0	0	0
T173	22170	0	0	0
T202	0	97	0	0
T223	0	8	0	0
T234	0	50	0	0
T267	0	61	0	0
T312	0	108	0	0
T319	0	82	0	0
T320	0	20	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441918716	1737	0	0
T6	108362	202	0	0
T14	0	21	0	0
T28	50485	0	0	0
T37	0	188	0	0
T51	55210	0	0	0
T54	17180	0	0	0
T67	148425	0	0	0
T91	21835	0	0	0
T101	19745	0	0	0
T136	89973	0	0	0
T172	11206	0	0	0
T173	22170	0	0	0
T202	0	65	0	0
T223	0	24	0	0
T234	0	19	0	0
T267	0	145	0	0
T312	0	99	0	0
T319	0	76	0	0
T320	0	55	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441918716	4221	0	0
T6	108362	126	0	0
T14	0	23	0	0
T28	50485	0	0	0
T37	0	224	0	0
T51	55210	0	0	0
T54	17180	0	0	0
T67	148425	0	0	0
T91	21835	0	0	0
T101	19745	0	0	0
T136	89973	0	0	0
T172	11206	0	0	0
T173	22170	0	0	0
T202	0	67	0	0
T223	0	49	0	0
T234	0	72	0	0
T267	0	111	0	0
T312	0	103	0	0
T319	0	143	0	0
T320	0	61	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441918716	4880	0	0
T6	108362	190	0	0
T14	0	22	0	0
T28	50485	0	0	0
T37	0	187	0	0
T51	55210	0	0	0
T54	17180	0	0	0
T67	148425	0	0	0
T74	0	31	0	0
T91	21835	0	0	0
T101	19745	0	0	0
T118	0	23	0	0
T136	89973	0	0	0
T172	11206	0	0	0
T173	22170	0	0	0
T183	0	2	0	0
T202	0	140	0	0
T223	0	35	0	0
T267	0	176	0	0
T321	0	41	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441918716	2375	0	0
T6	108362	162	0	0
T14	0	23	0	0
T28	50485	0	0	0
T37	0	198	0	0
T51	55210	0	0	0
T54	17180	0	0	0
T67	148425	0	0	0
T91	21835	0	0	0
T101	19745	0	0	0
T136	89973	0	0	0
T172	11206	0	0	0
T173	22170	0	0	0
T202	0	103	0	0
T223	0	46	0	0
T234	0	24	0	0
T267	0	137	0	0
T312	0	100	0	0
T319	0	81	0	0
T320	0	51	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441918716	2683	0	0
T6	108362	136	0	0
T14	0	19	0	0
T28	50485	0	0	0
T37	0	174	0	0
T51	55210	0	0	0
T54	17180	0	0	0
T67	148425	0	0	0
T91	21835	0	0	0
T101	19745	0	0	0
T136	89973	0	0	0
T172	11206	0	0	0
T173	22170	0	0	0
T202	0	148	0	0
T223	0	45	0	0
T234	0	39	0	0
T267	0	160	0	0
T312	0	104	0	0
T319	0	108	0	0
T320	0	96	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441918716	2633	0	0
T6	108362	173	0	0
T14	0	19	0	0
T28	50485	0	0	0
T37	0	181	0	0
T51	55210	0	0	0
T54	17180	0	0	0
T67	148425	0	0	0
T91	21835	0	0	0
T101	19745	0	0	0
T136	89973	0	0	0
T172	11206	0	0	0
T173	22170	0	0	0
T202	0	119	0	0
T223	0	33	0	0
T234	0	46	0	0
T267	0	87	0	0
T312	0	146	0	0
T319	0	128	0	0
T320	0	68	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441918716	2324	0	0
T6	108362	195	0	0
T14	0	48	0	0
T28	50485	0	0	0
T37	0	179	0	0
T51	55210	0	0	0
T54	17180	0	0	0
T67	148425	0	0	0
T91	21835	0	0	0
T101	19745	0	0	0
T136	89973	0	0	0
T172	11206	0	0	0
T173	22170	0	0	0
T202	0	88	0	0
T223	0	52	0	0
T234	0	28	0	0
T267	0	97	0	0
T312	0	85	0	0
T319	0	109	0	0
T320	0	45	0	0