Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.23	100.00	100.00		90.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.56	100.00	100.00	100.00	90.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.20	94.16	96.15	97.06		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.20	94.16	96.15	97.06		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.75	100.00	97.06		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.83	100.00	97.06	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.20	94.16	96.15	97.06		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T8,T5
1	Covered	T22,T23,T24

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T75,T129,T132
1	Covered	T75,T129,T132

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T8,T5
1	Covered	T2,T8,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T9

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T9

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	11	84.62
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T8,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T8,T5
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T179,T180
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T181,T182,T183
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T3,T9
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T75,T76,T77
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T1,T3,T9
CheckFailError	317	Covered	T75,T129,T132
FsmStateError	289	Covered	T2,T8,T5
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T9,T6,T136
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T1,T3,T6
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T75,T129,T132
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T2,T8,T5
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T1,T3,T9
NoError->CheckFailError	317	Covered	T75,T129,T132
NoError->FsmStateError	289	Covered	T2,T8,T5
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T51,T7,T13
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T3,T9
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T23,T24
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T8,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T5,T9,T29
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T5,T9,T29
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T8,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T75,T129,T132
1	0	Covered	T75,T129,T132
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T8,T5
1	0	Covered	T2,T8,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	438910216	438083137	0	0
DigestKnown_A	438910216	438083137	0	0
DigestOffsetMustBeRepresentable_A	1150	1150	0	0
EccErrorState_A	438910216	20650	0	0
ErrorKnown_A	438910216	438083137	0	0
FsmStateKnown_A	438910216	438083137	0	0
InitDoneKnown_A	438910216	438083137	0	0
InitReadLocksPartition_A	438910216	95482645	0	0
InitWriteLocksPartition_A	438910216	95482645	0	0
OffsetMustBeBlockAligned_A	1150	1150	0	0
OtpAddrKnown_A	438910216	438083137	0	0
OtpCmdKnown_A	438910216	438083137	0	0
OtpErrorState_A	438910216	0	0	0
OtpReqKnown_A	438910216	438083137	0	0
OtpSizeKnown_A	438910216	438083137	0	0
OtpWdataKnown_A	438910216	438083137	0	0
ReadLockPropagation_A	438910216	165518082	0	0
SizeMustBeBlockAligned_A	1150	1150	0	0
TlulGntKnown_A	438910216	438083137	0	0
TlulRdataKnown_A	438910216	438083137	0	0
TlulReadOnReadLock_A	438910216	7692	0	0
TlulRerrorKnown_A	438910216	438083137	0	0
TlulRvalidKnown_A	438910216	438083137	0	0
WriteLockPropagation_A	438910216	2338699	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	438910216	27296084	0	0
u_state_regs_A	438910216	438083137	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	20650	0	0
T18	509090	0	0	0
T26	16737	0	0	0
T42	13018	0	0	0
T75	12657	3399	0	0
T113	13459	0	0	0
T129	0	3932	0	0
T130	0	3867	0	0
T131	0	2922	0	0
T132	0	3503	0	0
T135	0	3027	0	0
T143	27437	0	0	0
T144	15245	0	0	0
T145	85559	0	0	0
T146	44058	0	0	0
T147	14508	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	95482645	0	0
T1	81170	556	0	0
T2	15627	5209	0	0
T3	106308	708	0	0
T4	31705	3815	0	0
T5	30724	23026	0	0
T8	14445	7105	0	0
T9	64180	46398	0	0
T10	14833	3682	0	0
T11	12041	4114	0	0
T12	9098	170	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	95482645	0	0
T1	81170	556	0	0
T2	15627	5209	0	0
T3	106308	708	0	0
T4	31705	3815	0	0
T5	30724	23026	0	0
T8	14445	7105	0	0
T9	64180	46398	0	0
T10	14833	3682	0	0
T11	12041	4114	0	0
T12	9098	170	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	165518082	0	0
T1	81170	28715	0	0
T2	15627	0	0	0
T3	106308	30324	0	0
T4	31705	0	0	0
T5	30724	0	0	0
T6	0	183651	0	0
T7	0	85494	0	0
T8	14445	0	0	0
T9	64180	49522	0	0
T10	14833	0	0	0
T11	12041	0	0	0
T12	9098	0	0	0
T28	0	4165	0	0
T51	0	4661	0	0
T67	0	20651	0	0
T136	0	80184	0	0
T172	0	1291	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	7692	0	0
T1	81170	2	0	0
T2	15627	0	0	0
T3	106308	5	0	0
T4	31705	0	0	0
T5	30724	19	0	0
T6	0	41	0	0
T8	14445	0	0	0
T9	64180	11	0	0
T10	14833	0	0	0
T11	12041	0	0	0
T12	9098	0	0	0
T28	0	1	0	0
T29	0	9	0	0
T51	0	2	0	0
T90	0	7	0	0
T91	0	3	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	2338699	0	0
T1	81170	20022	0	0
T2	15627	0	0	0
T3	106308	5059	0	0
T4	31705	0	0	0
T5	30724	0	0	0
T7	0	13797	0	0
T8	14445	0	0	0
T9	64180	0	0	0
T10	14833	0	0	0
T11	12041	0	0	0
T12	9098	0	0	0
T28	0	3821	0	0
T51	0	6407	0	0
T92	0	3048	0	0
T93	0	7425	0	0
T94	0	4228	0	0
T99	0	11727	0	0
T100	0	2823	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	27296084	0	0
T1	81170	62745	0	0
T2	15627	0	0	0
T3	106308	64677	0	0
T4	31705	0	0	0
T5	30724	0	0	0
T7	0	359380	0	0
T8	14445	0	0	0
T9	64180	3488	0	0
T10	14833	0	0	0
T11	12041	0	0	0
T12	9098	0	0	0
T28	0	30978	0	0
T51	0	27714	0	0
T57	0	3695	0	0
T92	0	72008	0	0
T98	0	3066	0	0
T136	0	4176	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T57,T61

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T67,T72,T133

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T8,T5
1	Covered	T22,T23,T24

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T75,T134,T135
1	Covered	T75,T134,T135

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T8,T5
1	Covered	T2,T8,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T9

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T9

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T8,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T8,T5
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T181,T182,T183
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T137,T138,T139
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T3,T6
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T98,T141,T184
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T75,T76,T77
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T3,T6
CheckFailError	317	Covered	T75,T134,T135
FsmStateError	289	Covered	T2,T8,T5
MacroEccCorrError	221	Covered	T10,T67,T57
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T6,T91,T136
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T3,T6
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T75,T134,T135
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T8,T5
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T10,T57,T61
MacroEccCorrError->NoError	235	Covered	T67,T72,T133
NoError->AccessError	256	Covered	T1,T3,T6
NoError->CheckFailError	317	Covered	T75,T134,T135
NoError->FsmStateError	289	Covered	T2,T8,T5
NoError->MacroEccCorrError	221	Covered	T10,T67,T57

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T10,T57,T61
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T137,T138,T139
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T7,T13,T100
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T3,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T67,T72,T133
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T98,T141,T184
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T23,T24
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T8,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T5,T9,T29
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T5,T9,T29
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T8,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T75,T134,T135
1	0	Covered	T75,T134,T135
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T8,T5
1	0	Covered	T2,T8,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	438910216	438083137	0	0
DigestKnown_A	438910216	438083137	0	0
DigestOffsetMustBeRepresentable_A	1150	1150	0	0
EccErrorState_A	438910216	9151	0	0
ErrorKnown_A	438910216	438083137	0	0
FsmStateKnown_A	438910216	438083137	0	0
InitDoneKnown_A	438910216	438083137	0	0
InitReadLocksPartition_A	438910216	95658141	0	0
InitWriteLocksPartition_A	438910216	95658141	0	0
OffsetMustBeBlockAligned_A	1150	1150	0	0
OtpAddrKnown_A	438910216	438083137	0	0
OtpCmdKnown_A	438910216	438083137	0	0
OtpErrorState_A	438910216	79	0	0
OtpReqKnown_A	438910216	438083137	0	0
OtpSizeKnown_A	438910216	438083137	0	0
OtpWdataKnown_A	438910216	438083137	0	0
ReadLockPropagation_A	438910216	164403121	0	0
SizeMustBeBlockAligned_A	1150	1150	0	0
TlulGntKnown_A	438910216	438083137	0	0
TlulRdataKnown_A	438910216	438083137	0	0
TlulReadOnReadLock_A	438910216	8017	0	0
TlulRerrorKnown_A	438910216	438083137	0	0
TlulRvalidKnown_A	438910216	438083137	0	0
WriteLockPropagation_A	438910216	2019195	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	438910216	24613783	0	0
u_state_regs_A	438910216	438083137	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	9151	0	0
T18	509090	0	0	0
T26	16737	0	0	0
T42	13018	0	0	0
T75	12657	3399	0	0
T113	13459	0	0	0
T134	0	2725	0	0
T135	0	3027	0	0
T143	27437	0	0	0
T144	15245	0	0	0
T145	85559	0	0	0
T146	44058	0	0	0
T147	14508	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	95658141	0	0
T1	81170	743	0	0
T2	15627	5260	0	0
T3	106308	861	0	0
T4	31705	3934	0	0
T5	30724	23060	0	0
T8	14445	7173	0	0
T9	64180	46466	0	0
T10	14833	3716	0	0
T11	12041	4148	0	0
T12	9098	221	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	95658141	0	0
T1	81170	743	0	0
T2	15627	5260	0	0
T3	106308	861	0	0
T4	31705	3934	0	0
T5	30724	23060	0	0
T8	14445	7173	0	0
T9	64180	46466	0	0
T10	14833	3716	0	0
T11	12041	4148	0	0
T12	9098	221	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	79	0	0
T13	320744	0	0	0
T22	103734	0	0	0
T57	14104	0	0	0
T61	13132	0	0	0
T92	83029	0	0	0
T93	69128	0	0	0
T98	86285	1	0	0
T99	48398	0	0	0
T100	65857	0	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T141	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T164	0	1	0	0
T169	16161	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	164403121	0	0
T1	81170	21345	0	0
T2	15627	0	0	0
T3	106308	38240	0	0
T4	31705	0	0	0
T5	30724	0	0	0
T6	0	185743	0	0
T7	0	82928	0	0
T8	14445	0	0	0
T9	64180	0	0	0
T10	14833	0	0	0
T11	12041	0	0	0
T12	9098	0	0	0
T28	0	6824	0	0
T51	0	6164	0	0
T67	0	23692	0	0
T91	0	8617	0	0
T102	0	2543	0	0
T136	0	80176	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	8017	0	0
T1	81170	6	0	0
T2	15627	0	0	0
T3	106308	11	0	0
T4	31705	0	0	0
T5	30724	21	0	0
T6	0	31	0	0
T8	14445	0	0	0
T9	64180	8	0	0
T10	14833	0	0	0
T11	12041	0	0	0
T12	9098	0	0	0
T29	0	14	0	0
T51	0	3	0	0
T90	0	4	0	0
T91	0	6	0	0
T173	0	11	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	2019195	0	0
T1	81170	8502	0	0
T2	15627	0	0	0
T3	106308	0	0	0
T4	31705	0	0	0
T5	30724	0	0	0
T7	0	13687	0	0
T8	14445	0	0	0
T9	64180	0	0	0
T10	14833	0	0	0
T11	12041	0	0	0
T12	9098	0	0	0
T28	0	7967	0	0
T72	0	18354	0	0
T74	0	10539	0	0
T92	0	4617	0	0
T94	0	4060	0	0
T96	0	3516	0	0
T100	0	2856	0	0
T124	0	5837	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	24613783	0	0
T1	81170	62575	0	0
T2	15627	0	0	0
T3	106308	78210	0	0
T4	31705	0	0	0
T5	30724	0	0	0
T7	0	325839	0	0
T8	14445	0	0	0
T9	64180	3454	0	0
T10	14833	0	0	0
T11	12041	0	0	0
T12	9098	0	0	0
T28	0	30859	0	0
T51	0	27578	0	0
T92	0	71736	0	0
T93	0	52650	0	0
T100	0	54512	0	0
T136	0	4142	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T57

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T98,T128,T72

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T8,T5
1	Covered	T22,T23,T24

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T75,T129,T134
1	Covered	T75,T129,T134

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T8,T5
1	Covered	T2,T8,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00110110000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T28,T136

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T28,T136

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T8,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T8,T5
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T181,T182,T183
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T137,T140,T138
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T3,T9
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T166,T168,T185
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T75,T76,T77
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T3,T9
CheckFailError	317	Covered	T75,T129,T134
FsmStateError	289	Covered	T2,T8,T5
MacroEccCorrError	221	Covered	T2,T10,T98
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T9,T6,T91
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T3,T6
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T75,T129,T134
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T8,T5
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T2,T10,T98
MacroEccCorrError->NoError	235	Covered	T98,T128,T72
NoError->AccessError	256	Covered	T1,T3,T9
NoError->CheckFailError	317	Covered	T75,T129,T134
NoError->FsmStateError	289	Covered	T8,T5,T11
NoError->MacroEccCorrError	221	Covered	T2,T10,T98

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T28,T136
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T57
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T140,T158,T159
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T51,T7,T94
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T3,T9
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T98,T128,T72
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T166,T168,T185
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T23,T24
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T8,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T8,T5,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T8,T5,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T8,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T75,T129,T134
1	0	Covered	T75,T129,T134
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T8,T5
1	0	Covered	T2,T8,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	438910216	438083137	0	0
DigestKnown_A	438910216	438083137	0	0
DigestOffsetMustBeRepresentable_A	1150	1150	0	0
EccErrorState_A	438910216	16586	0	0
ErrorKnown_A	438910216	438083137	0	0
FsmStateKnown_A	438910216	438083137	0	0
InitDoneKnown_A	438910216	438083137	0	0
InitReadLocksPartition_A	438910216	95832408	0	0
InitWriteLocksPartition_A	438910216	95832408	0	0
OffsetMustBeBlockAligned_A	1150	1150	0	0
OtpAddrKnown_A	438910216	438083137	0	0
OtpCmdKnown_A	438910216	438083137	0	0
OtpErrorState_A	438910216	54	0	0
OtpReqKnown_A	438910216	438083137	0	0
OtpSizeKnown_A	438910216	438083137	0	0
OtpWdataKnown_A	438910216	438083137	0	0
ReadLockPropagation_A	438910216	161600819	0	0
SizeMustBeBlockAligned_A	1150	1150	0	0
TlulGntKnown_A	438910216	438083137	0	0
TlulRdataKnown_A	438910216	438083137	0	0
TlulReadOnReadLock_A	438910216	8112	0	0
TlulRerrorKnown_A	438910216	438083137	0	0
TlulRvalidKnown_A	438910216	438083137	0	0
WriteLockPropagation_A	438910216	1069920	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	438910216	16906292	0	0
u_state_regs_A	438910216	438083137	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	16586	0	0
T18	509090	0	0	0
T26	16737	0	0	0
T42	13018	0	0	0
T75	12657	3399	0	0
T113	13459	0	0	0
T129	0	3932	0	0
T132	0	3503	0	0
T134	0	2725	0	0
T135	0	3027	0	0
T143	27437	0	0	0
T144	15245	0	0	0
T145	85559	0	0	0
T146	44058	0	0	0
T147	14508	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	95832408	0	0
T1	81170	930	0	0
T2	15627	5311	0	0
T3	106308	1014	0	0
T4	31705	4053	0	0
T5	30724	23094	0	0
T8	14445	7241	0	0
T9	64180	46534	0	0
T10	14833	3750	0	0
T11	12041	4182	0	0
T12	9098	272	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	95832408	0	0
T1	81170	930	0	0
T2	15627	5311	0	0
T3	106308	1014	0	0
T4	31705	4053	0	0
T5	30724	23094	0	0
T8	14445	7241	0	0
T9	64180	46534	0	0
T10	14833	3750	0	0
T11	12041	4182	0	0
T12	9098	272	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	54	0	0
T25	15006	0	0	0
T73	36025	0	0	0
T95	76413	0	0	0
T96	69955	0	0	0
T138	12237	0	0	0
T139	9645	0	0	0
T140	14476	1	0	0
T147	0	1	0	0
T156	15041	0	0	0
T158	0	1	0	0
T159	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T170	7652	0	0	0
T171	8340	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	161600819	0	0
T1	81170	33039	0	0
T2	15627	0	0	0
T3	106308	26920	0	0
T4	31705	0	0	0
T5	30724	0	0	0
T6	0	102043	0	0
T8	14445	0	0	0
T9	64180	50179	0	0
T10	14833	0	0	0
T11	12041	0	0	0
T12	9098	0	0	0
T28	0	8136	0	0
T51	0	3185	0	0
T67	0	24684	0	0
T91	0	8615	0	0
T136	0	80165	0	0
T172	0	928	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	8112	0	0
T1	81170	6	0	0
T2	15627	0	0	0
T3	106308	5	0	0
T4	31705	0	0	0
T5	30724	15	0	0
T6	0	27	0	0
T8	14445	1	0	0
T9	64180	4	0	0
T10	14833	0	0	0
T11	12041	0	0	0
T12	9098	0	0	0
T29	0	11	0	0
T51	0	5	0	0
T90	0	6	0	0
T91	0	4	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	1069920	0	0
T7	615079	8111	0	0
T13	320744	0	0	0
T57	14104	0	0	0
T74	0	3509	0	0
T92	83029	3048	0	0
T93	0	7425	0	0
T94	0	2438	0	0
T96	0	545	0	0
T97	0	3702	0	0
T98	86285	0	0	0
T99	48398	0	0	0
T102	19537	0	0	0
T116	0	2398	0	0
T118	0	23547	0	0
T169	16161	0	0	0
T174	0	5005	0	0
T177	5896	0	0	0
T178	11131	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	16906292	0	0
T1	81170	62405	0	0
T2	15627	0	0	0
T3	106308	0	0	0
T4	31705	0	0	0
T5	30724	0	0	0
T7	0	149307	0	0
T8	14445	0	0	0
T9	64180	0	0	0
T10	14833	0	0	0
T11	12041	0	0	0
T12	9098	0	0	0
T28	0	22174	0	0
T92	0	71464	0	0
T93	0	52480	0	0
T94	0	48001	0	0
T98	0	2998	0	0
T99	0	30964	0	0
T100	0	54308	0	0
T136	0	4108	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0