Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.20	94.16	96.15	97.06		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.20	94.16	96.15	97.06		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T125,T126,T127

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T67,T128,T72

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T8,T5
1	Covered	T22,T23,T24

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T129,T130,T131
1	Covered	T129,T130,T131

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T8,T5
1	Covered	T8,T5,T9

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T8,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T8,T5,T9
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T137,T138,T139
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T2,T103,T140
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T3,T91
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T98,T142,T166
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T75,T76,T77
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T3,T91
CheckFailError	317	Covered	T129,T130,T131
FsmStateError	289	Covered	T8,T5,T9
MacroEccCorrError	221	Covered	T67,T125,T128
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T91,T7,T13
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T3,T91
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T129,T130,T131
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T8,T5,T9
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T125,T141,T126
MacroEccCorrError->NoError	235	Covered	T67,T128,T72
NoError->AccessError	256	Covered	T1,T3,T91
NoError->CheckFailError	317	Covered	T129,T130,T131
NoError->FsmStateError	289	Covered	T8,T5,T9
NoError->MacroEccCorrError	221	Covered	T67,T125,T128

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T125,T126,T127
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T2,T103,T186
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T7,T100,T94
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T3,T91
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T67,T128,T72
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T98,T142,T166
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T23,T24
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T8,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T8,T5,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T8,T5,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T8,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T129,T130,T131
1	0	Covered	T129,T130,T131
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T8,T5,T9
1	0	Covered	T2,T8,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	438910216	438083137	0	0
DigestKnown_A	438910216	438083137	0	0
DigestOffsetMustBeRepresentable_A	1150	1150	0	0
EccErrorState_A	438910216	10721	0	0
ErrorKnown_A	438910216	438083137	0	0
FsmStateKnown_A	438910216	438083137	0	0
InitDoneKnown_A	438910216	438083137	0	0
InitReadLocksPartition_A	438910216	96005755	0	0
InitWriteLocksPartition_A	438910216	96005755	0	0
OffsetMustBeBlockAligned_A	1150	1150	0	0
OtpAddrKnown_A	438910216	438083137	0	0
OtpCmdKnown_A	438910216	438083137	0	0
OtpErrorState_A	438910216	49	0	0
OtpReqKnown_A	438910216	438083137	0	0
OtpSizeKnown_A	438910216	438083137	0	0
OtpWdataKnown_A	438910216	438083137	0	0
ReadLockPropagation_A	438910216	171179977	0	0
SizeMustBeBlockAligned_A	1150	1150	0	0
TlulGntKnown_A	438910216	438083137	0	0
TlulRdataKnown_A	438910216	438083137	0	0
TlulReadOnReadLock_A	438910216	8035	0	0
TlulRerrorKnown_A	438910216	438083137	0	0
TlulRvalidKnown_A	438910216	438083137	0	0
WriteLockPropagation_A	438910216	1904074	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	438910216	23348689	0	0
u_state_regs_A	438910216	438083137	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	10721	0	0
T40	17725	0	0	0
T129	10157	3932	0	0
T130	0	3867	0	0
T131	0	2922	0	0
T148	16116	0	0	0
T149	14889	0	0	0
T150	11860	0	0	0
T151	10125	0	0	0
T152	9389	0	0	0
T153	15465	0	0	0
T154	13270	0	0	0
T155	14879	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	96005755	0	0
T1	81170	1117	0	0
T2	15627	5352	0	0
T3	106308	1167	0	0
T4	31705	4172	0	0
T5	30724	23128	0	0
T8	14445	7309	0	0
T9	64180	46602	0	0
T10	14833	3784	0	0
T11	12041	4216	0	0
T12	9098	323	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	96005755	0	0
T1	81170	1117	0	0
T2	15627	5352	0	0
T3	106308	1167	0	0
T4	31705	4172	0	0
T5	30724	23128	0	0
T8	14445	7309	0	0
T9	64180	46602	0	0
T10	14833	3784	0	0
T11	12041	4216	0	0
T12	9098	323	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	49	0	0
T2	15627	1	0	0
T3	106308	0	0	0
T4	31705	0	0	0
T5	30724	0	0	0
T8	14445	0	0	0
T9	64180	0	0	0
T10	14833	0	0	0
T11	12041	0	0	0
T12	9098	0	0	0
T29	45768	0	0	0
T98	0	1	0	0
T103	0	1	0	0
T142	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	171179977	0	0
T1	81170	28257	0	0
T2	15627	0	0	0
T3	106308	24075	0	0
T4	31705	0	0	0
T5	30724	0	0	0
T6	0	180989	0	0
T7	0	82514	0	0
T8	14445	0	0	0
T9	64180	0	0	0
T10	14833	0	0	0
T11	12041	0	0	0
T12	9098	0	0	0
T28	0	3997	0	0
T51	0	3445	0	0
T67	0	26471	0	0
T91	0	8613	0	0
T98	0	2334	0	0
T172	0	924	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	8035	0	0
T1	81170	6	0	0
T2	15627	0	0	0
T3	106308	8	0	0
T4	31705	0	0	0
T5	30724	15	0	0
T6	0	27	0	0
T8	14445	3	0	0
T9	64180	11	0	0
T10	14833	0	0	0
T11	12041	0	0	0
T12	9098	0	0	0
T29	0	13	0	0
T51	0	1	0	0
T90	0	7	0	0
T91	0	7	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	1904074	0	0
T1	81170	9617	0	0
T2	15627	0	0	0
T3	106308	5312	0	0
T4	31705	0	0	0
T5	30724	0	0	0
T7	0	10719	0	0
T8	14445	0	0	0
T9	64180	0	0	0
T10	14833	0	0	0
T11	12041	0	0	0
T12	9098	0	0	0
T28	0	3202	0	0
T72	0	10592	0	0
T74	0	8351	0	0
T92	0	2118	0	0
T93	0	3954	0	0
T96	0	613	0	0
T100	0	8531	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	23348689	0	0
T1	81170	62235	0	0
T2	15627	4052	0	0
T3	106308	77972	0	0
T4	31705	0	0	0
T5	30724	0	0	0
T7	0	348543	0	0
T8	14445	0	0	0
T9	64180	3386	0	0
T10	14833	0	0	0
T11	12041	0	0	0
T12	9098	0	0	0
T28	0	30621	0	0
T51	0	38808	0	0
T92	0	71192	0	0
T93	0	52310	0	0
T136	0	4074	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T61,T25,T104

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T67,T98,T121

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T8,T5
1	Covered	T22,T23,T24

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T75,T135,T130
1	Covered	T75,T135,T130

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T8,T5
1	Covered	T2,T8,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T11,T51

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T11,T51

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T8,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T8,T5,T9
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T137,T140,T138
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T2,T11,T103
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T3,T9
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T98,T184,T185
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T75,T76,T77
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T3,T9
CheckFailError	317	Covered	T75,T135,T130
FsmStateError	289	Covered	T2,T8,T5
MacroEccCorrError	221	Covered	T67,T98,T61
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T9,T6,T136
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T3,T6
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T75,T135,T130
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T8,T5
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T61,T25,T192
MacroEccCorrError->NoError	235	Covered	T67,T98,T121
NoError->AccessError	256	Covered	T1,T3,T9
NoError->CheckFailError	317	Covered	T75,T135,T130
NoError->FsmStateError	289	Covered	T2,T8,T5
NoError->MacroEccCorrError	221	Covered	T67,T98,T61

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T51
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T61,T25,T104
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T11,T125,T126
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T7,T13,T100
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T3,T9
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T67,T98,T121
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T98,T184,T185
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T23,T24
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T8,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T8,T5,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T8,T5,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T8,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T75,T135,T130
1	0	Covered	T75,T135,T130
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T8,T5
1	0	Covered	T2,T8,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	438910216	438083137	0	0
DigestKnown_A	438910216	438083137	0	0
DigestOffsetMustBeRepresentable_A	1150	1150	0	0
EccErrorState_A	438910216	10293	0	0
ErrorKnown_A	438910216	438083137	0	0
FsmStateKnown_A	438910216	438083137	0	0
InitDoneKnown_A	438910216	438083137	0	0
InitReadLocksPartition_A	438910216	96178138	0	0
InitWriteLocksPartition_A	438910216	96178138	0	0
OffsetMustBeBlockAligned_A	1150	1150	0	0
OtpAddrKnown_A	438910216	438083137	0	0
OtpCmdKnown_A	438910216	438083137	0	0
OtpErrorState_A	438910216	45	0	0
OtpReqKnown_A	438910216	438083137	0	0
OtpSizeKnown_A	438910216	438083137	0	0
OtpWdataKnown_A	438910216	438083137	0	0
ReadLockPropagation_A	438910216	164747349	0	0
SizeMustBeBlockAligned_A	1150	1150	0	0
TlulGntKnown_A	438910216	438083137	0	0
TlulRdataKnown_A	438910216	438083137	0	0
TlulReadOnReadLock_A	438910216	7795	0	0
TlulRerrorKnown_A	438910216	438083137	0	0
TlulRvalidKnown_A	438910216	438083137	0	0
WriteLockPropagation_A	438910216	1014070	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	438910216	11332820	0	0
u_state_regs_A	438910216	438083137	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	10293	0	0
T18	509090	0	0	0
T26	16737	0	0	0
T42	13018	0	0	0
T75	12657	3399	0	0
T113	13459	0	0	0
T130	0	3867	0	0
T135	0	3027	0	0
T143	27437	0	0	0
T144	15245	0	0	0
T145	85559	0	0	0
T146	44058	0	0	0
T147	14508	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	96178138	0	0
T1	81170	1304	0	0
T2	15627	5386	0	0
T3	106308	1320	0	0
T4	31705	4291	0	0
T5	30724	23162	0	0
T8	14445	7377	0	0
T9	64180	46670	0	0
T10	14833	3818	0	0
T11	12041	4240	0	0
T12	9098	374	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	96178138	0	0
T1	81170	1304	0	0
T2	15627	5386	0	0
T3	106308	1320	0	0
T4	31705	4291	0	0
T5	30724	23162	0	0
T8	14445	7377	0	0
T9	64180	46670	0	0
T10	14833	3818	0	0
T11	12041	4240	0	0
T12	9098	374	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	45	0	0
T6	108362	0	0	0
T11	12041	1	0	0
T12	9098	0	0	0
T28	50485	0	0	0
T29	45768	0	0	0
T33	12650	0	0	0
T51	55210	0	0	0
T90	21181	0	0	0
T91	21835	0	0	0
T98	0	1	0	0
T125	0	1	0	0
T126	0	1	0	0
T172	11206	0	0	0
T184	0	1	0	0
T185	0	1	0	0
T193	0	1	0	0
T194	0	1	0	0
T195	0	1	0	0
T196	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	164747349	0	0
T1	81170	36478	0	0
T2	15627	0	0	0
T3	106308	24777	0	0
T4	31705	0	0	0
T5	30724	0	0	0
T6	0	107363	0	0
T7	0	85631	0	0
T8	14445	0	0	0
T9	64180	50168	0	0
T10	14833	0	0	0
T11	12041	0	0	0
T12	9098	0	0	0
T28	0	3985	0	0
T51	0	5030	0	0
T67	0	13628	0	0
T136	0	80158	0	0
T172	0	1277	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	7795	0	0
T1	81170	5	0	0
T2	15627	0	0	0
T3	106308	5	0	0
T4	31705	0	0	0
T5	30724	18	0	0
T6	0	27	0	0
T8	14445	1	0	0
T9	64180	10	0	0
T10	14833	0	0	0
T11	12041	0	0	0
T12	9098	0	0	0
T28	0	1	0	0
T29	0	15	0	0
T90	0	4	0	0
T91	0	10	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	1014070	0	0
T3	106308	27091	0	0
T4	31705	0	0	0
T5	30724	0	0	0
T7	0	11680	0	0
T8	14445	0	0	0
T9	64180	0	0	0
T10	14833	0	0	0
T11	12041	0	0	0
T12	9098	0	0	0
T29	45768	0	0	0
T90	21181	0	0	0
T95	0	8124	0	0
T116	0	16676	0	0
T118	0	17557	0	0
T175	0	8784	0	0
T176	0	1949	0	0
T197	0	7632	0	0
T198	0	303741	0	0
T199	0	13178	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	11332820	0	0
T3	106308	91969	0	0
T4	31705	0	0	0
T5	30724	0	0	0
T7	0	194153	0	0
T8	14445	0	0	0
T9	64180	0	0	0
T10	14833	0	0	0
T11	12041	3312	0	0
T12	9098	0	0	0
T29	45768	0	0	0
T51	0	38621	0	0
T74	0	86302	0	0
T90	21181	0	0	0
T95	0	57532	0	0
T124	0	42833	0	0
T125	0	2473	0	0
T128	0	52980	0	0
T200	0	27754	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438910216	438083137	0	0
T1	81170	80413	0	0
T2	15627	15385	0	0
T3	106308	105134	0	0
T4	31705	31164	0	0
T5	30724	30507	0	0
T8	14445	14192	0	0
T9	64180	63873	0	0
T10	14833	14585	0	0
T11	12041	11824	0	0
T12	9098	8875	0	0