Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.18	94.16	96.15	96.98		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	475152057	8710637	0	0
check_regwen_rd_A	475152057	3390	0	0
check_timeout_rd_A	475152057	2057	0	0
check_trigger_regwen_rd_A	475152057	3242	0	0
consistency_check_period_rd_A	475152057	3441	0	0
creator_sw_cfg_read_lock_rd_A	475152057	2341	0	0
direct_access_address_rd_A	475152057	1683	0	0
direct_access_wdata_0_rd_A	475152057	1180	0	0
direct_access_wdata_1_rd_A	475152057	1371	0	0
integrity_check_period_rd_A	475152057	3327	0	0
intr_enable_rd_A	475152057	4057	0	0
owner_sw_cfg_read_lock_rd_A	475152057	2260	0	0
rot_creator_auth_codesign_read_lock_rd_A	475152057	2279	0	0
rot_creator_auth_state_read_lock_rd_A	475152057	2027	0	0
vendor_test_read_lock_rd_A	475152057	2270	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475152057	8710637	0	0
T6	128920	26709	0	0
T7	116530	33323	0	0
T12	108143	308219	0	0
T15	0	107562	0	0
T16	0	102743	0	0
T26	0	195618	0	0
T27	745284	0	0	0
T37	0	102828	0	0
T44	24510	0	0	0
T70	0	150376	0	0
T72	20506	0	0	0
T73	11475	0	0	0
T79	51892	0	0	0
T106	11495	0	0	0
T110	25518	0	0	0
T113	0	93015	0	0
T274	0	40918	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475152057	3390	0	0
T6	128920	24	0	0
T7	116530	0	0	0
T12	108143	0	0	0
T15	0	84	0	0
T16	0	106	0	0
T27	745284	0	0	0
T44	24510	0	0	0
T72	20506	0	0	0
T73	11475	0	0	0
T79	51892	0	0	0
T106	11495	0	0	0
T110	25518	0	0	0
T132	0	56	0	0
T172	0	61	0	0
T213	0	51	0	0
T247	0	160	0	0
T274	0	37	0	0
T346	0	129	0	0
T347	0	92	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475152057	2057	0	0
T6	128920	26	0	0
T7	116530	0	0	0
T12	108143	0	0	0
T15	0	96	0	0
T16	0	98	0	0
T27	745284	0	0	0
T44	24510	0	0	0
T72	20506	0	0	0
T73	11475	0	0	0
T79	51892	0	0	0
T106	11495	0	0	0
T110	25518	0	0	0
T132	0	48	0	0
T172	0	65	0	0
T213	0	127	0	0
T247	0	196	0	0
T274	0	41	0	0
T346	0	171	0	0
T347	0	93	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475152057	3242	0	0
T13	33583	0	0	0
T15	554738	130	0	0
T16	543369	101	0	0
T38	154631	0	0	0
T41	21262	0	0	0
T49	14331	0	0	0
T50	12378	0	0	0
T77	12801	0	0	0
T111	41013	0	0	0
T132	0	32	0	0
T172	0	48	0	0
T213	0	76	0	0
T220	9426	0	0	0
T247	0	184	0	0
T274	0	65	0	0
T346	0	114	0	0
T347	0	54	0	0
T348	0	38	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475152057	3441	0	0
T6	128920	20	0	0
T7	116530	0	0	0
T12	108143	0	0	0
T15	0	95	0	0
T16	0	96	0	0
T27	745284	0	0	0
T44	24510	0	0	0
T72	20506	0	0	0
T73	11475	0	0	0
T79	51892	0	0	0
T106	11495	0	0	0
T110	25518	0	0	0
T132	0	73	0	0
T172	0	47	0	0
T213	0	78	0	0
T247	0	168	0	0
T274	0	97	0	0
T346	0	89	0	0
T347	0	121	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475152057	2341	0	0
T6	128920	14	0	0
T7	116530	0	0	0
T12	108143	0	0	0
T15	0	140	0	0
T16	0	152	0	0
T27	745284	0	0	0
T44	24510	0	0	0
T72	20506	0	0	0
T73	11475	0	0	0
T79	51892	0	0	0
T106	11495	0	0	0
T110	25518	0	0	0
T132	0	40	0	0
T172	0	94	0	0
T213	0	82	0	0
T247	0	213	0	0
T274	0	60	0	0
T346	0	114	0	0
T347	0	103	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475152057	1683	0	0
T6	128920	33	0	0
T7	116530	0	0	0
T12	108143	0	0	0
T15	0	99	0	0
T16	0	136	0	0
T27	745284	0	0	0
T44	24510	0	0	0
T72	20506	0	0	0
T73	11475	0	0	0
T79	51892	0	0	0
T106	11495	0	0	0
T110	25518	0	0	0
T132	0	33	0	0
T172	0	39	0	0
T213	0	89	0	0
T247	0	206	0	0
T274	0	36	0	0
T346	0	127	0	0
T347	0	98	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475152057	1180	0	0
T6	128920	19	0	0
T7	116530	0	0	0
T12	108143	0	0	0
T15	0	86	0	0
T16	0	119	0	0
T27	745284	0	0	0
T44	24510	0	0	0
T72	20506	0	0	0
T73	11475	0	0	0
T79	51892	0	0	0
T106	11495	0	0	0
T110	25518	0	0	0
T132	0	4	0	0
T172	0	35	0	0
T213	0	43	0	0
T247	0	148	0	0
T274	0	27	0	0
T346	0	89	0	0
T347	0	98	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475152057	1371	0	0
T6	128920	2	0	0
T7	116530	0	0	0
T12	108143	0	0	0
T15	0	93	0	0
T16	0	139	0	0
T27	745284	0	0	0
T44	24510	0	0	0
T72	20506	0	0	0
T73	11475	0	0	0
T79	51892	0	0	0
T106	11495	0	0	0
T110	25518	0	0	0
T132	0	50	0	0
T172	0	57	0	0
T213	0	34	0	0
T247	0	197	0	0
T274	0	62	0	0
T346	0	119	0	0
T347	0	60	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475152057	3327	0	0
T6	128920	9	0	0
T7	116530	0	0	0
T12	108143	0	0	0
T15	0	161	0	0
T16	0	108	0	0
T27	745284	0	0	0
T44	24510	0	0	0
T72	20506	0	0	0
T73	11475	0	0	0
T79	51892	0	0	0
T106	11495	0	0	0
T110	25518	0	0	0
T132	0	50	0	0
T172	0	58	0	0
T213	0	84	0	0
T247	0	182	0	0
T274	0	56	0	0
T346	0	119	0	0
T347	0	73	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475152057	4057	0	0
T6	128920	12	0	0
T7	116530	0	0	0
T9	611165	12	0	0
T10	34475	0	0	0
T11	4201	0	0	0
T12	108143	0	0	0
T15	0	191	0	0
T16	0	209	0	0
T27	745284	12	0	0
T72	20506	0	0	0
T79	51892	0	0	0
T106	11495	0	0	0
T132	0	55	0	0
T172	0	52	0	0
T247	0	154	0	0
T274	0	54	0	0
T346	0	141	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475152057	2260	0	0
T6	128920	16	0	0
T7	116530	0	0	0
T12	108143	0	0	0
T15	0	116	0	0
T16	0	137	0	0
T27	745284	0	0	0
T44	24510	0	0	0
T72	20506	0	0	0
T73	11475	0	0	0
T79	51892	0	0	0
T106	11495	0	0	0
T110	25518	0	0	0
T132	0	39	0	0
T172	0	63	0	0
T213	0	61	0	0
T247	0	216	0	0
T274	0	52	0	0
T346	0	126	0	0
T347	0	106	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475152057	2279	0	0
T6	128920	17	0	0
T7	116530	0	0	0
T12	108143	0	0	0
T15	0	145	0	0
T16	0	220	0	0
T27	745284	0	0	0
T44	24510	0	0	0
T72	20506	0	0	0
T73	11475	0	0	0
T79	51892	0	0	0
T106	11495	0	0	0
T110	25518	0	0	0
T132	0	26	0	0
T172	0	76	0	0
T213	0	61	0	0
T247	0	251	0	0
T274	0	81	0	0
T346	0	139	0	0
T347	0	43	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475152057	2027	0	0
T6	128920	19	0	0
T7	116530	0	0	0
T12	108143	0	0	0
T15	0	125	0	0
T16	0	127	0	0
T27	745284	0	0	0
T44	24510	0	0	0
T72	20506	0	0	0
T73	11475	0	0	0
T79	51892	0	0	0
T106	11495	0	0	0
T110	25518	0	0	0
T132	0	40	0	0
T172	0	49	0	0
T213	0	77	0	0
T247	0	226	0	0
T274	0	58	0	0
T346	0	144	0	0
T347	0	83	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475152057	2270	0	0
T6	128920	23	0	0
T7	116530	0	0	0
T12	108143	0	0	0
T15	0	104	0	0
T16	0	131	0	0
T27	745284	0	0	0
T44	24510	0	0	0
T72	20506	0	0	0
T73	11475	0	0	0
T79	51892	0	0	0
T106	11495	0	0	0
T110	25518	0	0	0
T132	0	45	0	0
T172	0	38	0	0
T213	0	33	0	0
T247	0	236	0	0
T274	0	57	0	0
T346	0	100	0	0
T347	0	114	0	0