Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

25736339

1

T1

251119

T2

5750

T3

345557

full_word

8423407

1

T1

78444

T2

5049

T3

104387

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34159506	1			T1	329563		T2	10799		T3	449944
auto[TlIntgErrCmd]	92	1			T270	4		T271	8		T272	6
auto[TlIntgErrData]	68	1			T270	4		T271	4		T272	3
auto[TlIntgErrBoth]	80	1			T270	2		T271	8		T272	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9732491

1

T1

48694

T2

9817

T3

93827

auto[1]

24427255

1

T1

280869

T2

982

T3

356117

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6121706	1			T1	27198		T2	5167		T3	58464
auto[TlIntgErrNone]	partial	auto[1]	19614425	1			T1	223921		T2	583		T3	287093
auto[TlIntgErrNone]	full_word	auto[0]	3610677	1			T1	21496		T2	4650		T3	35363
auto[TlIntgErrNone]	full_word	auto[1]	4812698	1			T1	56948		T2	399		T3	69024
auto[TlIntgErrCmd]	partial	auto[0]	30	1			T270	1		T271	2		T272	3
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T270	3		T271	6		T272	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T276	1		T353	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T272	1		T352	1		T353	1
auto[TlIntgErrData]	partial	auto[0]	23	1			T270	1		T271	2		T272	2
auto[TlIntgErrData]	partial	auto[1]	33	1			T270	3		T271	1		T272	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T271	1		T348	1		T351	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T349	1		T351	1		T350	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T271	4		T348	3		T351	4
auto[TlIntgErrBoth]	partial	auto[1]	30	1			T270	2		T271	4		T272	1
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T351	1		T357	1		T358	2
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T351	1		T352	1		T359	2