Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.23	94.16	96.15	97.22		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	495891741	8307259	0	0
check_regwen_rd_A	495891741	3466	0	0
check_timeout_rd_A	495891741	3033	0	0
check_trigger_regwen_rd_A	495891741	3397	0	0
consistency_check_period_rd_A	495891741	3617	0	0
creator_sw_cfg_read_lock_rd_A	495891741	2942	0	0
direct_access_address_rd_A	495891741	2341	0	0
direct_access_wdata_0_rd_A	495891741	1534	0	0
direct_access_wdata_1_rd_A	495891741	1621	0	0
integrity_check_period_rd_A	495891741	3363	0	0
intr_enable_rd_A	495891741	4468	0	0
owner_sw_cfg_read_lock_rd_A	495891741	2602	0	0
rot_creator_auth_codesign_read_lock_rd_A	495891741	2792	0	0
rot_creator_auth_state_read_lock_rd_A	495891741	2522	0	0
vendor_test_read_lock_rd_A	495891741	2699	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495891741	8307259	0	0
T1	318614	98933	0	0
T2	29106	0	0	0
T3	839433	126704	0	0
T4	14464	0	0	0
T5	155310	0	0	0
T6	199542	59791	0	0
T7	16990	0	0	0
T8	83214	0	0	0
T9	23839	0	0	0
T10	24904	0	0	0
T11	0	30910	0	0
T13	0	150204	0	0
T33	0	226796	0	0
T143	0	92273	0	0
T146	0	85763	0	0
T171	0	26229	0	0
T193	0	34172	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495891741	3466	0	0
T3	839433	174	0	0
T4	14464	0	0	0
T5	155310	0	0	0
T6	199542	0	0	0
T7	16990	0	0	0
T8	83214	0	0	0
T9	23839	0	0	0
T10	24904	0	0	0
T23	60893	0	0	0
T109	14372	0	0	0
T143	0	95	0	0
T147	0	89	0	0
T171	0	27	0	0
T249	0	87	0	0
T281	0	98	0	0
T328	0	81	0	0
T329	0	55	0	0
T330	0	91	0	0
T331	0	57	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495891741	3033	0	0
T3	839433	132	0	0
T4	14464	0	0	0
T5	155310	0	0	0
T6	199542	0	0	0
T7	16990	0	0	0
T8	83214	0	0	0
T9	23839	0	0	0
T10	24904	0	0	0
T23	60893	0	0	0
T109	14372	0	0	0
T143	0	77	0	0
T147	0	150	0	0
T171	0	20	0	0
T249	0	115	0	0
T281	0	12	0	0
T328	0	138	0	0
T329	0	113	0	0
T330	0	78	0	0
T331	0	46	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495891741	3397	0	0
T3	839433	138	0	0
T4	14464	0	0	0
T5	155310	0	0	0
T6	199542	0	0	0
T7	16990	0	0	0
T8	83214	0	0	0
T9	23839	0	0	0
T10	24904	0	0	0
T23	60893	0	0	0
T109	14372	0	0	0
T143	0	54	0	0
T147	0	107	0	0
T171	0	21	0	0
T249	0	73	0	0
T281	0	41	0	0
T328	0	94	0	0
T329	0	35	0	0
T330	0	63	0	0
T331	0	31	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495891741	3617	0	0
T3	839433	164	0	0
T4	14464	0	0	0
T5	155310	0	0	0
T6	199542	0	0	0
T7	16990	0	0	0
T8	83214	0	0	0
T9	23839	0	0	0
T10	24904	0	0	0
T23	60893	0	0	0
T109	14372	0	0	0
T143	0	39	0	0
T147	0	134	0	0
T171	0	42	0	0
T249	0	189	0	0
T281	0	52	0	0
T328	0	125	0	0
T329	0	35	0	0
T330	0	86	0	0
T331	0	46	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495891741	2942	0	0
T3	839433	187	0	0
T4	14464	0	0	0
T5	155310	0	0	0
T6	199542	0	0	0
T7	16990	0	0	0
T8	83214	0	0	0
T9	23839	0	0	0
T10	24904	0	0	0
T23	60893	0	0	0
T109	14372	0	0	0
T143	0	90	0	0
T147	0	141	0	0
T171	0	27	0	0
T249	0	119	0	0
T281	0	67	0	0
T328	0	111	0	0
T329	0	56	0	0
T330	0	121	0	0
T331	0	29	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495891741	2341	0	0
T3	839433	114	0	0
T4	14464	0	0	0
T5	155310	0	0	0
T6	199542	0	0	0
T7	16990	0	0	0
T8	83214	0	0	0
T9	23839	0	0	0
T10	24904	0	0	0
T23	60893	0	0	0
T109	14372	0	0	0
T143	0	85	0	0
T147	0	94	0	0
T171	0	36	0	0
T249	0	137	0	0
T281	0	76	0	0
T328	0	135	0	0
T329	0	71	0	0
T330	0	73	0	0
T331	0	28	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495891741	1534	0	0
T3	839433	122	0	0
T4	14464	0	0	0
T5	155310	0	0	0
T6	199542	0	0	0
T7	16990	0	0	0
T8	83214	0	0	0
T9	23839	0	0	0
T10	24904	0	0	0
T23	60893	0	0	0
T109	14372	0	0	0
T143	0	20	0	0
T147	0	54	0	0
T171	0	5	0	0
T249	0	79	0	0
T281	0	25	0	0
T328	0	74	0	0
T329	0	31	0	0
T330	0	63	0	0
T331	0	37	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495891741	1621	0	0
T3	839433	145	0	0
T4	14464	0	0	0
T5	155310	0	0	0
T6	199542	0	0	0
T7	16990	0	0	0
T8	83214	0	0	0
T9	23839	0	0	0
T10	24904	0	0	0
T23	60893	0	0	0
T109	14372	0	0	0
T143	0	59	0	0
T147	0	104	0	0
T171	0	14	0	0
T249	0	123	0	0
T281	0	19	0	0
T328	0	96	0	0
T329	0	56	0	0
T330	0	35	0	0
T331	0	47	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495891741	3363	0	0
T3	839433	130	0	0
T4	14464	0	0	0
T5	155310	0	0	0
T6	199542	0	0	0
T7	16990	0	0	0
T8	83214	0	0	0
T9	23839	0	0	0
T10	24904	0	0	0
T23	60893	0	0	0
T109	14372	0	0	0
T143	0	88	0	0
T147	0	124	0	0
T171	0	23	0	0
T249	0	106	0	0
T281	0	56	0	0
T328	0	139	0	0
T329	0	35	0	0
T330	0	91	0	0
T331	0	33	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495891741	4468	0	0
T3	839433	157	0	0
T4	14464	0	0	0
T5	155310	0	0	0
T6	199542	0	0	0
T7	16990	0	0	0
T8	83214	0	0	0
T9	23839	0	0	0
T10	24904	0	0	0
T23	60893	0	0	0
T109	14372	0	0	0
T134	0	16	0	0
T143	0	88	0	0
T147	0	129	0	0
T171	0	24	0	0
T241	0	5	0	0
T249	0	139	0	0
T328	0	136	0	0
T329	0	67	0	0
T332	0	42	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495891741	2602	0	0
T3	839433	174	0	0
T4	14464	0	0	0
T5	155310	0	0	0
T6	199542	0	0	0
T7	16990	0	0	0
T8	83214	0	0	0
T9	23839	0	0	0
T10	24904	0	0	0
T23	60893	0	0	0
T109	14372	0	0	0
T143	0	60	0	0
T147	0	118	0	0
T171	0	3	0	0
T249	0	122	0	0
T281	0	75	0	0
T328	0	94	0	0
T329	0	67	0	0
T330	0	49	0	0
T331	0	77	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495891741	2792	0	0
T3	839433	144	0	0
T4	14464	0	0	0
T5	155310	0	0	0
T6	199542	0	0	0
T7	16990	0	0	0
T8	83214	0	0	0
T9	23839	0	0	0
T10	24904	0	0	0
T23	60893	0	0	0
T109	14372	0	0	0
T143	0	47	0	0
T147	0	87	0	0
T171	0	26	0	0
T249	0	88	0	0
T281	0	63	0	0
T328	0	166	0	0
T329	0	53	0	0
T330	0	75	0	0
T331	0	44	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495891741	2522	0	0
T3	839433	141	0	0
T4	14464	0	0	0
T5	155310	0	0	0
T6	199542	0	0	0
T7	16990	0	0	0
T8	83214	0	0	0
T9	23839	0	0	0
T10	24904	0	0	0
T23	60893	0	0	0
T109	14372	0	0	0
T143	0	58	0	0
T147	0	118	0	0
T171	0	9	0	0
T249	0	98	0	0
T281	0	20	0	0
T328	0	119	0	0
T329	0	42	0	0
T330	0	68	0	0
T331	0	28	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495891741	2699	0	0
T3	839433	156	0	0
T4	14464	0	0	0
T5	155310	0	0	0
T6	199542	0	0	0
T7	16990	0	0	0
T8	83214	0	0	0
T9	23839	0	0	0
T10	24904	0	0	0
T23	60893	0	0	0
T109	14372	0	0	0
T143	0	69	0	0
T147	0	109	0	0
T171	0	12	0	0
T249	0	108	0	0
T281	0	52	0	0
T328	0	140	0	0
T329	0	81	0	0
T330	0	97	0	0
T331	0	43	0	0