Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.14	94.16	96.15	96.79		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	477494860	8667106	0	0
check_regwen_rd_A	477494860	2459	0	0
check_timeout_rd_A	477494860	2077	0	0
check_trigger_regwen_rd_A	477494860	2402	0	0
consistency_check_period_rd_A	477494860	2752	0	0
creator_sw_cfg_read_lock_rd_A	477494860	2119	0	0
direct_access_address_rd_A	477494860	1716	0	0
direct_access_wdata_0_rd_A	477494860	1366	0	0
direct_access_wdata_1_rd_A	477494860	1529	0	0
integrity_check_period_rd_A	477494860	2537	0	0
intr_enable_rd_A	477494860	3395	0	0
owner_sw_cfg_read_lock_rd_A	477494860	1890	0	0
rot_creator_auth_codesign_read_lock_rd_A	477494860	2132	0	0
rot_creator_auth_state_read_lock_rd_A	477494860	1989	0	0
vendor_test_read_lock_rd_A	477494860	2095	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477494860	8667106	0	0
T7	128088	283548	0	0
T8	23191	0	0	0
T9	0	321617	0	0
T14	0	51568	0	0
T19	0	153467	0	0
T43	33166	0	0	0
T46	13888	0	0	0
T56	39229	0	0	0
T61	0	88252	0	0
T97	69147	0	0	0
T130	44164	0	0	0
T177	0	112217	0	0
T179	11222	0	0	0
T180	10289	0	0	0
T186	57638	0	0	0
T217	0	74075	0	0
T248	0	88427	0	0
T267	0	56541	0	0
T268	0	123206	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477494860	2459	0	0
T21	132070	34	0	0
T36	369058	0	0	0
T54	15539	0	0	0
T111	12039	0	0	0
T119	0	191	0	0
T167	10726	0	0	0
T168	17107	0	0	0
T251	0	48	0	0
T253	15628	0	0	0
T272	0	49	0	0
T281	24241	0	0	0
T282	60354	0	0	0
T309	0	31	0	0
T310	0	73	0	0
T311	0	62	0	0
T312	0	44	0	0
T313	0	25	0	0
T314	0	92	0	0
T315	6490	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477494860	2077	0	0
T21	132070	35	0	0
T36	369058	0	0	0
T54	15539	0	0	0
T111	12039	0	0	0
T119	0	143	0	0
T167	10726	0	0	0
T168	17107	0	0	0
T251	0	61	0	0
T253	15628	0	0	0
T272	0	49	0	0
T281	24241	0	0	0
T282	60354	0	0	0
T309	0	18	0	0
T310	0	110	0	0
T311	0	94	0	0
T312	0	88	0	0
T313	0	27	0	0
T314	0	123	0	0
T315	6490	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477494860	2402	0	0
T21	132070	25	0	0
T36	369058	0	0	0
T54	15539	0	0	0
T111	12039	0	0	0
T119	0	184	0	0
T167	10726	0	0	0
T168	17107	0	0	0
T251	0	72	0	0
T253	15628	0	0	0
T272	0	26	0	0
T281	24241	0	0	0
T282	60354	0	0	0
T309	0	32	0	0
T310	0	74	0	0
T311	0	54	0	0
T312	0	35	0	0
T313	0	36	0	0
T314	0	83	0	0
T315	6490	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477494860	2752	0	0
T21	132070	21	0	0
T36	369058	0	0	0
T54	15539	0	0	0
T111	12039	0	0	0
T119	0	168	0	0
T167	10726	0	0	0
T168	17107	0	0	0
T251	0	75	0	0
T253	15628	0	0	0
T272	0	21	0	0
T281	24241	0	0	0
T282	60354	0	0	0
T309	0	49	0	0
T310	0	97	0	0
T311	0	69	0	0
T312	0	58	0	0
T313	0	35	0	0
T314	0	113	0	0
T315	6490	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477494860	2119	0	0
T21	132070	20	0	0
T36	369058	0	0	0
T54	15539	0	0	0
T111	12039	0	0	0
T119	0	175	0	0
T167	10726	0	0	0
T168	17107	0	0	0
T251	0	100	0	0
T253	15628	0	0	0
T272	0	29	0	0
T281	24241	0	0	0
T282	60354	0	0	0
T309	0	36	0	0
T310	0	52	0	0
T311	0	72	0	0
T312	0	74	0	0
T313	0	15	0	0
T314	0	74	0	0
T315	6490	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477494860	1716	0	0
T21	132070	21	0	0
T36	369058	0	0	0
T54	15539	0	0	0
T111	12039	0	0	0
T119	0	130	0	0
T167	10726	0	0	0
T168	17107	0	0	0
T251	0	60	0	0
T253	15628	0	0	0
T272	0	42	0	0
T281	24241	0	0	0
T282	60354	0	0	0
T309	0	59	0	0
T310	0	110	0	0
T311	0	62	0	0
T312	0	42	0	0
T313	0	19	0	0
T314	0	93	0	0
T315	6490	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477494860	1366	0	0
T21	132070	13	0	0
T36	369058	0	0	0
T54	15539	0	0	0
T111	12039	0	0	0
T119	0	116	0	0
T167	10726	0	0	0
T168	17107	0	0	0
T251	0	47	0	0
T253	15628	0	0	0
T272	0	14	0	0
T281	24241	0	0	0
T282	60354	0	0	0
T309	0	7	0	0
T310	0	123	0	0
T311	0	59	0	0
T312	0	22	0	0
T313	0	9	0	0
T314	0	115	0	0
T315	6490	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477494860	1529	0	0
T21	132070	9	0	0
T36	369058	0	0	0
T54	15539	0	0	0
T111	12039	0	0	0
T119	0	100	0	0
T167	10726	0	0	0
T168	17107	0	0	0
T251	0	88	0	0
T253	15628	0	0	0
T272	0	47	0	0
T281	24241	0	0	0
T282	60354	0	0	0
T309	0	21	0	0
T310	0	105	0	0
T311	0	76	0	0
T312	0	29	0	0
T313	0	19	0	0
T314	0	96	0	0
T315	6490	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477494860	2537	0	0
T21	132070	14	0	0
T36	369058	0	0	0
T54	15539	0	0	0
T111	12039	0	0	0
T119	0	144	0	0
T167	10726	0	0	0
T168	17107	0	0	0
T251	0	68	0	0
T253	15628	0	0	0
T272	0	32	0	0
T281	24241	0	0	0
T282	60354	0	0	0
T309	0	28	0	0
T310	0	101	0	0
T311	0	125	0	0
T312	0	58	0	0
T313	0	39	0	0
T314	0	55	0	0
T315	6490	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477494860	3395	0	0
T11	143261	31	0	0
T12	103330	0	0	0
T13	103101	0	0	0
T17	4974	0	0	0
T21	0	30	0	0
T29	52570	0	0	0
T42	47366	0	0	0
T66	0	80	0	0
T67	11314	0	0	0
T100	17060	0	0	0
T101	15492	0	0	0
T102	24581	0	0	0
T119	0	174	0	0
T239	0	25	0	0
T251	0	64	0	0
T272	0	44	0	0
T309	0	35	0	0
T310	0	119	0	0
T316	0	5	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477494860	1890	0	0
T21	132070	25	0	0
T36	369058	0	0	0
T54	15539	0	0	0
T111	12039	0	0	0
T119	0	106	0	0
T167	10726	0	0	0
T168	17107	0	0	0
T251	0	53	0	0
T253	15628	0	0	0
T272	0	41	0	0
T281	24241	0	0	0
T282	60354	0	0	0
T309	0	35	0	0
T310	0	75	0	0
T311	0	48	0	0
T312	0	54	0	0
T313	0	41	0	0
T314	0	82	0	0
T315	6490	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477494860	2132	0	0
T21	132070	20	0	0
T36	369058	0	0	0
T54	15539	0	0	0
T111	12039	0	0	0
T119	0	226	0	0
T167	10726	0	0	0
T168	17107	0	0	0
T251	0	56	0	0
T253	15628	0	0	0
T272	0	30	0	0
T281	24241	0	0	0
T282	60354	0	0	0
T309	0	35	0	0
T310	0	93	0	0
T311	0	97	0	0
T312	0	40	0	0
T313	0	5	0	0
T314	0	61	0	0
T315	6490	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477494860	1989	0	0
T21	132070	48	0	0
T36	369058	0	0	0
T54	15539	0	0	0
T111	12039	0	0	0
T119	0	156	0	0
T167	10726	0	0	0
T168	17107	0	0	0
T251	0	72	0	0
T253	15628	0	0	0
T272	0	30	0	0
T281	24241	0	0	0
T282	60354	0	0	0
T309	0	47	0	0
T310	0	107	0	0
T311	0	99	0	0
T312	0	48	0	0
T313	0	16	0	0
T314	0	52	0	0
T315	6490	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477494860	2095	0	0
T21	132070	23	0	0
T36	369058	0	0	0
T54	15539	0	0	0
T111	12039	0	0	0
T119	0	207	0	0
T167	10726	0	0	0
T168	17107	0	0	0
T251	0	77	0	0
T253	15628	0	0	0
T272	0	45	0	0
T281	24241	0	0	0
T282	60354	0	0	0
T309	0	45	0	0
T310	0	101	0	0
T311	0	66	0	0
T312	0	39	0	0
T313	0	28	0	0
T314	0	81	0	0
T315	6490	0	0	0