Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.23	100.00	100.00		85.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.73	100.00	100.00	100.00	85.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.14	94.16	96.15	96.79		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.14	94.16	96.15	96.79		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.75	100.00	97.06		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.83	100.00	97.06	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.14	94.16	96.15	96.79		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T2,T3,T6
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T22,T23,T24

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T131,T133,T132
1	Covered	T131,T133,T132

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T2,T3,T6

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T11
1	1	Covered	T2,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T11,T12

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T11,T12

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	10	76.92
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T6
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T6
ReadWaitSt	252	Covered	T2,T3,T6
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T6
IdleSt->ReadSt	236	Covered	T2,T3,T6
InitSt->ErrorSt	315	Not Covered
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T138,T152,T184
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T11,T12,T29
ReadSt->ReadWaitSt	252	Covered	T2,T3,T6
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T2,T3,T6
ResetSt->ErrorSt	315	Covered	T76,T77,T78
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T11,T12,T29
CheckFailError	317	Covered	T131,T133,T132
FsmStateError	289	Covered	T2,T3,T6
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T7,T9,T15
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T11,T12,T29
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T131,T133,T132
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T2,T3,T6
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T11,T12,T29
NoError->CheckFailError	317	Covered	T131,T133,T132
NoError->FsmStateError	289	Covered	T2,T3,T6
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T6
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T6
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T11,T29,T97
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T11,T12,T29
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T23,T24
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T4,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T4,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T6
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T131,T133,T132
1	0	Covered	T131,T133,T132
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	474529611	473670376	0	0
DigestKnown_A	474529611	473670376	0	0
DigestOffsetMustBeRepresentable_A	1149	1149	0	0
EccErrorState_A	474529611	9960	0	0
ErrorKnown_A	474529611	473670376	0	0
FsmStateKnown_A	474529611	473670376	0	0
InitDoneKnown_A	474529611	473670376	0	0
InitReadLocksPartition_A	474529611	83156771	0	0
InitWriteLocksPartition_A	474529611	83156771	0	0
OffsetMustBeBlockAligned_A	1149	1149	0	0
OtpAddrKnown_A	474529611	473670376	0	0
OtpCmdKnown_A	474529611	473670376	0	0
OtpErrorState_A	474529611	0	0	0
OtpReqKnown_A	474529611	473670376	0	0
OtpSizeKnown_A	474529611	473670376	0	0
OtpWdataKnown_A	474529611	473670376	0	0
ReadLockPropagation_A	474529611	187093294	0	0
SizeMustBeBlockAligned_A	1149	1149	0	0
TlulGntKnown_A	474529611	473670376	0	0
TlulRdataKnown_A	474529611	473670376	0	0
TlulReadOnReadLock_A	474529611	7214	0	0
TlulRerrorKnown_A	474529611	473670376	0	0
TlulRvalidKnown_A	474529611	473670376	0	0
WriteLockPropagation_A	474529611	2021945	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	474529611	25804347	0	0
u_state_regs_A	474529611	473670376	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	9960	0	0
T131	11857	2324	0	0
T132	0	2184	0	0
T133	0	2978	0	0
T143	0	2474	0	0
T153	13119	0	0	0
T154	12873	0	0	0
T155	33174	0	0	0
T156	492336	0	0	0
T157	247086	0	0	0
T158	31593	0	0	0
T159	309757	0	0	0
T160	179932	0	0	0
T161	41980	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	83156771	0	0
T1	29945	9154	0	0
T2	13312	4223	0	0
T3	52976	41142	0	0
T4	118435	103740	0	0
T5	85309	6724	0	0
T6	13837	4649	0	0
T10	29553	2198	0	0
T11	143261	75415	0	0
T12	103330	7745	0	0
T13	103101	89380	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	83156771	0	0
T1	29945	9154	0	0
T2	13312	4223	0	0
T3	52976	41142	0	0
T4	118435	103740	0	0
T5	85309	6724	0	0
T6	13837	4649	0	0
T10	29553	2198	0	0
T11	143261	75415	0	0
T12	103330	7745	0	0
T13	103101	89380	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	187093294	0	0
T7	0	110539	0	0
T11	143261	139389	0	0
T12	103330	38134	0	0
T13	103101	95207	0	0
T17	4974	0	0	0
T29	52570	2064	0	0
T42	47366	3002	0	0
T43	0	725	0	0
T56	0	2825	0	0
T67	11314	0	0	0
T97	0	5762	0	0
T100	17060	0	0	0
T101	15492	0	0	0
T102	24581	0	0	0
T179	0	3092	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	7214	0	0
T3	52976	12	0	0
T4	118435	15	0	0
T5	85309	0	0	0
T6	13837	0	0	0
T7	0	53	0	0
T10	29553	0	0	0
T11	143261	44	0	0
T12	103330	10	0	0
T13	103101	10	0	0
T29	52570	1	0	0
T67	11314	0	0	0
T100	0	7	0	0
T130	0	3	0	0
T179	0	1	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	2021945	0	0
T11	143261	102106	0	0
T12	103330	15177	0	0
T13	103101	0	0	0
T16	0	2351	0	0
T17	4974	0	0	0
T18	0	11717	0	0
T29	52570	0	0	0
T42	47366	3236	0	0
T52	0	8242	0	0
T66	0	31862	0	0
T67	11314	0	0	0
T97	0	1551	0	0
T98	0	12665	0	0
T100	17060	0	0	0
T101	15492	0	0	0
T102	24581	0	0	0
T103	0	17394	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	25804347	0	0
T3	52976	3687	0	0
T4	118435	0	0	0
T5	85309	0	0	0
T6	13837	0	0	0
T10	29553	0	0	0
T11	143261	923354	0	0
T12	103330	75191	0	0
T13	103101	0	0	0
T18	0	356909	0	0
T29	52570	43644	0	0
T42	0	39243	0	0
T43	0	24031	0	0
T66	0	221307	0	0
T67	11314	0	0	0
T97	0	60827	0	0
T130	0	3273	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T95,T134,T28

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T5,T12,T130

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T22,T23,T24

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T77,T131,T135
1	Covered	T77,T131,T135

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T2,T3,T6

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T2,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T6

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T12,T29

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T12,T29

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T6
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T6
ReadWaitSt	252	Covered	T2,T3,T6
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T6
IdleSt->ReadSt	236	Covered	T2,T3,T6
InitSt->ErrorSt	315	Covered	T138,T152,T184
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T93,T162,T164
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T11,T12,T13
ReadSt->ReadWaitSt	252	Covered	T2,T3,T6
ReadWaitSt->ErrorSt	276	Covered	T5,T187,T188
ReadWaitSt->IdleSt	270	Covered	T2,T3,T6
ResetSt->ErrorSt	315	Covered	T76,T77,T78
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T11,T12,T13
CheckFailError	317	Covered	T77,T131,T135
FsmStateError	289	Covered	T2,T3,T6
MacroEccCorrError	221	Covered	T5,T12,T130
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T13,T7,T186
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T11,T12,T13
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T77,T131,T135
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T6
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T130,T95,T189
MacroEccCorrError->NoError	235	Covered	T5,T12,T43
NoError->AccessError	256	Covered	T11,T12,T13
NoError->CheckFailError	317	Covered	T77,T131,T135
NoError->FsmStateError	289	Covered	T2,T3,T6
NoError->MacroEccCorrError	221	Covered	T5,T12,T130

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T29
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T95,T134,T28
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T93,T162,T164
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T6
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T6
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T11,T29,T42
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T11,T12,T13
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T5,T12,T130
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T5,T187,T188
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T23,T24
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T6
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T77,T131,T135
1	0	Covered	T77,T131,T135
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	474529611	473670376	0	0
DigestKnown_A	474529611	473670376	0	0
DigestOffsetMustBeRepresentable_A	1149	1149	0	0
EccErrorState_A	474529611	11421	0	0
ErrorKnown_A	474529611	473670376	0	0
FsmStateKnown_A	474529611	473670376	0	0
InitDoneKnown_A	474529611	473670376	0	0
InitReadLocksPartition_A	474529611	83337790	0	0
InitWriteLocksPartition_A	474529611	83337790	0	0
OffsetMustBeBlockAligned_A	1149	1149	0	0
OtpAddrKnown_A	474529611	473670376	0	0
OtpCmdKnown_A	474529611	473670376	0	0
OtpErrorState_A	474529611	75	0	0
OtpReqKnown_A	474529611	473670376	0	0
OtpSizeKnown_A	474529611	473670376	0	0
OtpWdataKnown_A	474529611	473670376	0	0
ReadLockPropagation_A	474529611	189546703	0	0
SizeMustBeBlockAligned_A	1149	1149	0	0
TlulGntKnown_A	474529611	473670376	0	0
TlulRdataKnown_A	474529611	473670376	0	0
TlulReadOnReadLock_A	474529611	7604	0	0
TlulRerrorKnown_A	474529611	473670376	0	0
TlulRvalidKnown_A	474529611	473670376	0	0
WriteLockPropagation_A	474529611	2336544	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	474529611	25281084	0	0
u_state_regs_A	474529611	473670376	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	11421	0	0
T28	15129	0	0	0
T77	11429	3661	0	0
T131	0	2324	0	0
T135	0	2962	0	0
T143	0	2474	0	0
T145	12620	0	0	0
T146	11707	0	0	0
T147	156894	0	0	0
T148	24138	0	0	0
T149	11828	0	0	0
T150	14935	0	0	0
T151	10662	0	0	0
T152	16966	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	83337790	0	0
T1	29945	9239	0	0
T2	13312	4274	0	0
T3	52976	41193	0	0
T4	118435	103791	0	0
T5	85309	6930	0	0
T6	13837	4700	0	0
T10	29553	2317	0	0
T11	143261	77217	0	0
T12	103330	7898	0	0
T13	103101	89414	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	83337790	0	0
T1	29945	9239	0	0
T2	13312	4274	0	0
T3	52976	41193	0	0
T4	118435	103791	0	0
T5	85309	6930	0	0
T6	13837	4700	0	0
T10	29553	2317	0	0
T11	143261	77217	0	0
T12	103330	7898	0	0
T13	103101	89414	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	75	0	0
T5	85309	1	0	0
T10	29553	0	0	0
T11	143261	0	0	0
T12	103330	0	0	0
T13	103101	0	0	0
T17	4974	0	0	0
T29	52570	0	0	0
T67	11314	0	0	0
T93	0	1	0	0
T100	17060	0	0	0
T101	15492	0	0	0
T162	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	189546703	0	0
T7	0	110496	0	0
T11	143261	161700	0	0
T12	103330	26583	0	0
T13	103101	94755	0	0
T17	4974	0	0	0
T29	52570	2484	0	0
T42	47366	3675	0	0
T67	11314	0	0	0
T97	0	5652	0	0
T100	17060	9833	0	0
T101	15492	0	0	0
T102	24581	0	0	0
T130	0	1821	0	0
T179	0	3089	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	7604	0	0
T3	52976	7	0	0
T4	118435	14	0	0
T5	85309	1	0	0
T6	13837	0	0	0
T7	0	44	0	0
T10	29553	0	0	0
T11	143261	46	0	0
T12	103330	6	0	0
T13	103101	22	0	0
T29	52570	1	0	0
T42	0	1	0	0
T67	11314	0	0	0
T100	0	3	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	2336544	0	0
T11	143261	108539	0	0
T12	103330	0	0	0
T13	103101	0	0	0
T15	0	16627	0	0
T17	4974	0	0	0
T18	0	28381	0	0
T29	52570	543	0	0
T42	47366	0	0	0
T51	0	3946	0	0
T52	0	6878	0	0
T66	0	36712	0	0
T67	11314	0	0	0
T97	0	2242	0	0
T98	0	15420	0	0
T100	17060	0	0	0
T101	15492	0	0	0
T102	24581	0	0	0
T103	0	4678	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	25281084	0	0
T11	143261	895032	0	0
T12	103330	75072	0	0
T13	103101	0	0	0
T17	4974	0	0	0
T18	0	303265	0	0
T29	52570	37610	0	0
T42	47366	27666	0	0
T43	0	23895	0	0
T66	0	220916	0	0
T67	11314	0	0	0
T97	0	60657	0	0
T100	17060	0	0	0
T101	15492	0	0	0
T102	24581	0	0	0
T130	0	3256	0	0
T186	0	2745	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T83,T136

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T5,T130,T56

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T22,T23,T24

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T133,T137,T132
1	Covered	T133,T137,T132

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T2,T3,T6

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T2,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00110110000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T11,T12

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T11,T12

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T6
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T6
ReadWaitSt	252	Covered	T2,T3,T6
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T6
IdleSt->ReadSt	236	Covered	T2,T3,T6
InitSt->ErrorSt	315	Covered	T138,T152,T184
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T93,T95,T162
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T11,T12,T100
ReadSt->ReadWaitSt	252	Covered	T2,T3,T6
ReadWaitSt->ErrorSt	276	Covered	T139,T175,T188
ReadWaitSt->IdleSt	270	Covered	T2,T3,T6
ResetSt->ErrorSt	315	Covered	T76,T77,T78
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T11,T12,T100
CheckFailError	317	Covered	T133,T137,T132
FsmStateError	289	Covered	T2,T3,T6
MacroEccCorrError	221	Covered	T6,T5,T130
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T100,T7,T186
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T11,T12,T100
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T133,T137,T132
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T6
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T6,T130,T83
MacroEccCorrError->NoError	235	Covered	T5,T56,T51
NoError->AccessError	256	Covered	T11,T12,T100
NoError->CheckFailError	317	Covered	T133,T137,T132
NoError->FsmStateError	289	Covered	T2,T3,T4
NoError->MacroEccCorrError	221	Covered	T6,T5,T130

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T6,T83,T136
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T95,T163,T150
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T6
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T6
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T11,T29,T97
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T11,T12,T100
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T5,T130,T56
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T139,T175,T188
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T23,T24
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T6
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T133,T137,T132
1	0	Covered	T133,T137,T132
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	474529611	473670376	0	0
DigestKnown_A	474529611	473670376	0	0
DigestOffsetMustBeRepresentable_A	1149	1149	0	0
EccErrorState_A	474529611	16855	0	0
ErrorKnown_A	474529611	473670376	0	0
FsmStateKnown_A	474529611	473670376	0	0
InitDoneKnown_A	474529611	473670376	0	0
InitReadLocksPartition_A	474529611	83517745	0	0
InitWriteLocksPartition_A	474529611	83517745	0	0
OffsetMustBeBlockAligned_A	1149	1149	0	0
OtpAddrKnown_A	474529611	473670376	0	0
OtpCmdKnown_A	474529611	473670376	0	0
OtpErrorState_A	474529611	51	0	0
OtpReqKnown_A	474529611	473670376	0	0
OtpSizeKnown_A	474529611	473670376	0	0
OtpWdataKnown_A	474529611	473670376	0	0
ReadLockPropagation_A	474529611	193548087	0	0
SizeMustBeBlockAligned_A	1149	1149	0	0
TlulGntKnown_A	474529611	473670376	0	0
TlulRdataKnown_A	474529611	473670376	0	0
TlulReadOnReadLock_A	474529611	7669	0	0
TlulRerrorKnown_A	474529611	473670376	0	0
TlulRvalidKnown_A	474529611	473670376	0	0
WriteLockPropagation_A	474529611	1003287	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	474529611	14025269	0	0
u_state_regs_A	474529611	473670376	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	16855	0	0
T55	14607	0	0	0
T120	14899	0	0	0
T132	0	2184	0	0
T133	12197	2978	0	0
T137	0	2227	0	0
T141	0	3409	0	0
T142	0	3269	0	0
T144	0	2788	0	0
T190	81137	0	0	0
T191	14243	0	0	0
T192	10402	0	0	0
T193	29440	0	0	0
T194	91333	0	0	0
T195	34247	0	0	0
T196	125308	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	83517745	0	0
T1	29945	9324	0	0
T2	13312	4325	0	0
T3	52976	41244	0	0
T4	118435	103842	0	0
T5	85309	7132	0	0
T6	13837	4751	0	0
T10	29553	2436	0	0
T11	143261	79019	0	0
T12	103330	8051	0	0
T13	103101	89448	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	83517745	0	0
T1	29945	9324	0	0
T2	13312	4325	0	0
T3	52976	41244	0	0
T4	118435	103842	0	0
T5	85309	7132	0	0
T6	13837	4751	0	0
T10	29553	2436	0	0
T11	143261	79019	0	0
T12	103330	8051	0	0
T13	103101	89448	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	51	0	0
T14	237667	0	0	0
T47	19039	0	0	0
T52	100949	0	0	0
T76	17166	0	0	0
T95	8784	1	0	0
T96	13911	0	0	0
T138	27520	0	0	0
T139	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T163	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T170	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T176	13085	0	0	0
T177	502281	0	0	0
T178	12288	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	193548087	0	0
T7	0	110449	0	0
T11	143261	172440	0	0
T12	103330	33734	0	0
T13	103101	0	0	0
T17	4974	0	0	0
T29	52570	1363	0	0
T42	47366	3284	0	0
T43	0	723	0	0
T56	0	949	0	0
T67	11314	0	0	0
T97	0	7014	0	0
T100	17060	9826	0	0
T101	15492	0	0	0
T102	24581	0	0	0
T179	0	2610	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	7669	0	0
T3	52976	8	0	0
T4	118435	15	0	0
T5	85309	1	0	0
T6	13837	0	0	0
T7	0	47	0	0
T10	29553	0	0	0
T11	143261	42	0	0
T12	103330	8	0	0
T13	103101	15	0	0
T29	52570	0	0	0
T42	0	3	0	0
T67	11314	0	0	0
T100	0	5	0	0
T179	0	1	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	1003287	0	0
T11	143261	49870	0	0
T12	103330	25305	0	0
T13	103101	0	0	0
T15	0	12014	0	0
T16	0	1164	0	0
T17	4974	0	0	0
T18	0	15795	0	0
T29	52570	0	0	0
T42	47366	0	0	0
T66	0	9677	0	0
T67	11314	0	0	0
T72	0	14585	0	0
T98	0	3260	0	0
T99	0	6167	0	0
T100	17060	0	0	0
T101	15492	0	0	0
T102	24581	0	0	0
T184	0	16100	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	14025269	0	0
T3	52976	3619	0	0
T4	118435	0	0	0
T5	85309	0	0	0
T6	13837	0	0	0
T10	29553	0	0	0
T11	143261	415074	0	0
T12	103330	74953	0	0
T13	103101	0	0	0
T18	0	264963	0	0
T29	52570	0	0	0
T66	0	69881	0	0
T67	11314	0	0	0
T95	0	3189	0	0
T97	0	60487	0	0
T130	0	3239	0	0
T138	0	2551	0	0
T186	0	2728	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474529611	473670376	0	0
T1	29945	29393	0	0
T2	13312	13028	0	0
T3	52976	52771	0	0
T4	118435	118163	0	0
T5	85309	84024	0	0
T6	13837	13605	0	0
T10	29553	28989	0	0
T11	143261	142378	0	0
T12	103330	102578	0	0
T13	103101	102831	0	0