Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

26645349

1

T1

965

T2

2238

T3

1096

full_word

8736365

1

T1

418

T2

2063

T3

255

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	35381364	1			T1	1383		T2	4301		T3	1351
auto[TlIntgErrCmd]	116	1			T257	4		T258	11		T259	10
auto[TlIntgErrData]	119	1			T257	7		T258	5		T259	7
auto[TlIntgErrBoth]	115	1			T257	9		T258	4		T259	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10329731

1

T1

1241

T2

3862

T3

1264

auto[1]

25051983

1

T1

142

T2

439

T3

87

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6539875	1			T1	887		T2	2001		T3	1042
auto[TlIntgErrNone]	partial	auto[1]	20105151	1			T1	78		T2	237		T3	54
auto[TlIntgErrNone]	full_word	auto[0]	3789702	1			T1	354		T2	1861		T3	222
auto[TlIntgErrNone]	full_word	auto[1]	4946636	1			T1	64		T2	202		T3	33
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T257	2		T258	4		T259	4
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T257	2		T258	6		T259	6
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T335	1		T340	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T258	1		T341	1		T342	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T257	2		T258	3		T259	3
auto[TlIntgErrData]	partial	auto[1]	58	1			T257	5		T258	1		T259	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T258	1		T333	1		T334	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T259	1		T333	2		T335	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T257	3		T258	3		T259	2
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T257	6		T259	1		T333	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T334	2		T343	1		T342	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T258	1		T334	1		T342	1