Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.18	94.16	96.15	96.98		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	474603455	8503384	0	0
check_regwen_rd_A	474603455	3732	0	0
check_timeout_rd_A	474603455	2936	0	0
check_trigger_regwen_rd_A	474603455	4012	0	0
consistency_check_period_rd_A	474603455	3761	0	0
creator_sw_cfg_read_lock_rd_A	474603455	2905	0	0
direct_access_address_rd_A	474603455	2088	0	0
direct_access_wdata_0_rd_A	474603455	1283	0	0
direct_access_wdata_1_rd_A	474603455	1439	0	0
integrity_check_period_rd_A	474603455	3649	0	0
intr_enable_rd_A	474603455	4621	0	0
owner_sw_cfg_read_lock_rd_A	474603455	2641	0	0
rot_creator_auth_codesign_read_lock_rd_A	474603455	2845	0	0
rot_creator_auth_state_read_lock_rd_A	474603455	2751	0	0
vendor_test_read_lock_rd_A	474603455	2670	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474603455	8503384	0	0
T7	282026	60784	0	0
T8	439723	72372	0	0
T9	196577	36346	0	0
T16	54747	0	0	0
T17	0	30698	0	0
T18	0	94146	0	0
T19	0	63715	0	0
T20	0	50492	0	0
T29	61958	0	0	0
T30	109001	0	0	0
T38	96563	0	0	0
T60	18220	0	0	0
T98	12239	0	0	0
T100	16236	0	0	0
T129	0	30932	0	0
T225	0	239649	0	0
T263	0	118322	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474603455	3732	0	0
T8	439723	62	0	0
T9	196577	74	0	0
T17	0	49	0	0
T34	14212	0	0	0
T38	96563	0	0	0
T60	18220	0	0	0
T93	107073	0	0	0
T94	63554	0	0	0
T100	16236	0	0	0
T101	204144	0	0	0
T129	0	45	0	0
T151	9367	0	0	0
T264	0	189	0	0
T313	0	23	0	0
T314	0	65	0	0
T315	0	38	0	0
T316	0	66	0	0
T317	0	58	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474603455	2936	0	0
T8	439723	136	0	0
T9	196577	53	0	0
T17	0	23	0	0
T34	14212	0	0	0
T38	96563	0	0	0
T60	18220	0	0	0
T93	107073	0	0	0
T94	63554	0	0	0
T100	16236	0	0	0
T101	204144	0	0	0
T129	0	60	0	0
T151	9367	0	0	0
T264	0	130	0	0
T313	0	21	0	0
T314	0	86	0	0
T315	0	47	0	0
T316	0	43	0	0
T317	0	102	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474603455	4012	0	0
T8	439723	131	0	0
T9	196577	63	0	0
T17	0	26	0	0
T34	14212	0	0	0
T38	96563	0	0	0
T60	18220	0	0	0
T93	107073	0	0	0
T94	63554	0	0	0
T100	16236	0	0	0
T101	204144	0	0	0
T129	0	48	0	0
T151	9367	0	0	0
T264	0	125	0	0
T313	0	9	0	0
T314	0	115	0	0
T315	0	80	0	0
T316	0	103	0	0
T317	0	59	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474603455	3761	0	0
T8	439723	126	0	0
T9	196577	53	0	0
T17	0	11	0	0
T34	14212	0	0	0
T38	96563	0	0	0
T60	18220	0	0	0
T93	107073	0	0	0
T94	63554	0	0	0
T100	16236	0	0	0
T101	204144	0	0	0
T129	0	53	0	0
T151	9367	0	0	0
T264	0	111	0	0
T313	0	8	0	0
T314	0	98	0	0
T315	0	42	0	0
T316	0	78	0	0
T317	0	106	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474603455	2905	0	0
T8	439723	141	0	0
T9	196577	36	0	0
T17	0	34	0	0
T34	14212	0	0	0
T38	96563	0	0	0
T60	18220	0	0	0
T93	107073	0	0	0
T94	63554	0	0	0
T100	16236	0	0	0
T101	204144	0	0	0
T129	0	41	0	0
T151	9367	0	0	0
T264	0	178	0	0
T313	0	38	0	0
T314	0	105	0	0
T315	0	37	0	0
T316	0	47	0	0
T317	0	128	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474603455	2088	0	0
T8	439723	115	0	0
T9	196577	60	0	0
T17	0	31	0	0
T34	14212	0	0	0
T38	96563	0	0	0
T60	18220	0	0	0
T93	107073	0	0	0
T94	63554	0	0	0
T100	16236	0	0	0
T101	204144	0	0	0
T129	0	35	0	0
T151	9367	0	0	0
T264	0	192	0	0
T313	0	41	0	0
T314	0	120	0	0
T315	0	66	0	0
T316	0	87	0	0
T317	0	62	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474603455	1283	0	0
T8	439723	94	0	0
T9	196577	34	0	0
T17	0	14	0	0
T34	14212	0	0	0
T38	96563	0	0	0
T60	18220	0	0	0
T93	107073	0	0	0
T94	63554	0	0	0
T100	16236	0	0	0
T101	204144	0	0	0
T129	0	27	0	0
T151	9367	0	0	0
T264	0	66	0	0
T314	0	47	0	0
T315	0	63	0	0
T316	0	73	0	0
T317	0	77	0	0
T318	0	27	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474603455	1439	0	0
T8	439723	60	0	0
T9	196577	8	0	0
T17	0	21	0	0
T34	14212	0	0	0
T38	96563	0	0	0
T60	18220	0	0	0
T93	107073	0	0	0
T94	63554	0	0	0
T100	16236	0	0	0
T101	204144	0	0	0
T129	0	37	0	0
T151	9367	0	0	0
T264	0	170	0	0
T313	0	19	0	0
T314	0	70	0	0
T315	0	9	0	0
T316	0	20	0	0
T317	0	68	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474603455	3649	0	0
T8	439723	81	0	0
T9	196577	29	0	0
T17	0	29	0	0
T34	14212	0	0	0
T38	96563	0	0	0
T60	18220	0	0	0
T93	107073	0	0	0
T94	63554	0	0	0
T100	16236	0	0	0
T101	204144	0	0	0
T129	0	42	0	0
T151	9367	0	0	0
T264	0	145	0	0
T313	0	13	0	0
T314	0	74	0	0
T315	0	72	0	0
T316	0	36	0	0
T317	0	50	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474603455	4621	0	0
T8	439723	132	0	0
T9	196577	91	0	0
T17	0	18	0	0
T34	14212	0	0	0
T38	96563	0	0	0
T60	18220	0	0	0
T93	107073	0	0	0
T94	63554	0	0	0
T99	0	6	0	0
T100	16236	0	0	0
T101	204144	0	0	0
T129	0	34	0	0
T151	9367	0	0	0
T264	0	205	0	0
T310	0	50	0	0
T313	0	25	0	0
T314	0	103	0	0
T319	0	41	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474603455	2641	0	0
T8	439723	102	0	0
T9	196577	41	0	0
T17	0	37	0	0
T34	14212	0	0	0
T38	96563	0	0	0
T60	18220	0	0	0
T93	107073	0	0	0
T94	63554	0	0	0
T100	16236	0	0	0
T101	204144	0	0	0
T129	0	30	0	0
T151	9367	0	0	0
T264	0	173	0	0
T313	0	25	0	0
T314	0	93	0	0
T315	0	52	0	0
T316	0	61	0	0
T317	0	67	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474603455	2845	0	0
T8	439723	127	0	0
T9	196577	56	0	0
T17	0	17	0	0
T34	14212	0	0	0
T38	96563	0	0	0
T60	18220	0	0	0
T93	107073	0	0	0
T94	63554	0	0	0
T100	16236	0	0	0
T101	204144	0	0	0
T129	0	42	0	0
T151	9367	0	0	0
T264	0	128	0	0
T313	0	20	0	0
T314	0	113	0	0
T315	0	54	0	0
T316	0	68	0	0
T317	0	48	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474603455	2751	0	0
T8	439723	84	0	0
T9	196577	41	0	0
T17	0	52	0	0
T34	14212	0	0	0
T38	96563	0	0	0
T60	18220	0	0	0
T93	107073	0	0	0
T94	63554	0	0	0
T100	16236	0	0	0
T101	204144	0	0	0
T129	0	46	0	0
T151	9367	0	0	0
T264	0	182	0	0
T313	0	38	0	0
T314	0	109	0	0
T315	0	44	0	0
T316	0	68	0	0
T317	0	80	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474603455	2670	0	0
T8	439723	107	0	0
T9	196577	56	0	0
T17	0	22	0	0
T34	14212	0	0	0
T38	96563	0	0	0
T60	18220	0	0	0
T93	107073	0	0	0
T94	63554	0	0	0
T100	16236	0	0	0
T101	204144	0	0	0
T129	0	42	0	0
T151	9367	0	0	0
T264	0	101	0	0
T313	0	18	0	0
T314	0	101	0	0
T315	0	57	0	0
T316	0	30	0	0
T317	0	74	0	0