Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.23	100.00	100.00		90.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.56	100.00	100.00	100.00	90.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.18	94.16	96.15	96.98		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.18	94.16	96.15	96.98		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.75	100.00	97.06		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.83	100.00	97.06	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.18	94.16	96.15	96.98		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T6,T11
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T23,T24,T25

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T153
1	Covered	T153

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T11

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T11

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T6,T11
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T6,T11
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T12

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T12

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	11	84.62
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T4
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T6,T11
ReadWaitSt	252	Covered	T1,T6,T11
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T4
IdleSt->ReadSt	236	Covered	T1,T6,T11
InitSt->ErrorSt	315	Covered	T195
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T196,T190,T140
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T11,T12
ReadSt->ReadWaitSt	252	Covered	T1,T6,T11
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T1,T6,T11
ResetSt->ErrorSt	315	Covered	T71,T72,T73
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T1,T11,T12
CheckFailError	317	Covered	T153
FsmStateError	289	Covered	T2,T3,T4
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T8,T9,T14
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T1,T11,T12
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T153
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T2,T3,T4
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T1,T11,T12
NoError->CheckFailError	317	Covered	T153
NoError->FsmStateError	289	Covered	T2,T3,T4
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T6,T11

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T6,T11

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T6,T11
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T6,T11
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T93,T15,T112
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T11,T12
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T6,T11
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T6,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T24,T25
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T153
1	0	Covered	T153
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	471208209	470337320	0	0
DigestKnown_A	471208209	470337320	0	0
DigestOffsetMustBeRepresentable_A	1150	1150	0	0
EccErrorState_A	471208209	2082	0	0
ErrorKnown_A	471208209	470337320	0	0
FsmStateKnown_A	471208209	470337320	0	0
InitDoneKnown_A	471208209	470337320	0	0
InitReadLocksPartition_A	471208209	92821757	0	0
InitWriteLocksPartition_A	471208209	92821757	0	0
OffsetMustBeBlockAligned_A	1150	1150	0	0
OtpAddrKnown_A	471208209	470337320	0	0
OtpCmdKnown_A	471208209	470337320	0	0
OtpErrorState_A	471208209	0	0	0
OtpReqKnown_A	471208209	470337320	0	0
OtpSizeKnown_A	471208209	470337320	0	0
OtpWdataKnown_A	471208209	470337320	0	0
ReadLockPropagation_A	471208209	196156882	0	0
SizeMustBeBlockAligned_A	1150	1150	0	0
TlulGntKnown_A	471208209	470337320	0	0
TlulRdataKnown_A	471208209	470337320	0	0
TlulReadOnReadLock_A	471208209	8256	0	0
TlulRerrorKnown_A	471208209	470337320	0	0
TlulRvalidKnown_A	471208209	470337320	0	0
WriteLockPropagation_A	471208209	2301458	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	471208209	28447321	0	0
u_state_regs_A	471208209	470337320	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	2082	0	0
T153	8446	2082	0	0
T164	10496	0	0	0
T165	28873	0	0	0
T166	90811	0	0	0
T167	64353	0	0	0
T168	22828	0	0	0
T169	130681	0	0	0
T170	13842	0	0	0
T171	73621	0	0	0
T172	10937	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	92821757	0	0
T1	11625	349	0	0
T2	38656	31152	0	0
T3	11965	1567	0	0
T4	88698	81833	0	0
T5	26615	920	0	0
T6	10710	4449	0	0
T10	11230	3190	0	0
T11	67376	3059	0	0
T12	55042	4303	0	0
T13	11151	3275	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	92821757	0	0
T1	11625	349	0	0
T2	38656	31152	0	0
T3	11965	1567	0	0
T4	88698	81833	0	0
T5	26615	920	0	0
T6	10710	4449	0	0
T10	11230	3190	0	0
T11	67376	3059	0	0
T12	55042	4303	0	0
T13	11151	3275	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	196156882	0	0
T1	11625	1812	0	0
T2	38656	31170	0	0
T3	11965	0	0	0
T4	88698	0	0	0
T5	26615	1185	0	0
T6	10710	0	0	0
T7	0	220211	0	0
T10	11230	0	0	0
T11	67376	13416	0	0
T12	55042	3292	0	0
T13	11151	0	0	0
T16	0	9919	0	0
T29	0	2127	0	0
T30	0	16423	0	0
T98	0	3754	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	8256	0	0
T1	11625	1	0	0
T2	38656	7	0	0
T3	11965	1	0	0
T4	88698	28	0	0
T5	26615	0	0	0
T6	10710	0	0	0
T7	0	22	0	0
T10	11230	0	0	0
T11	67376	1	0	0
T12	55042	4	0	0
T13	11151	0	0	0
T16	0	5	0	0
T29	0	4	0	0
T98	0	2	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	2301458	0	0
T7	282026	0	0	0
T8	439723	0	0	0
T11	67376	9093	0	0
T12	55042	0	0	0
T13	11151	0	0	0
T16	54747	3603	0	0
T29	61958	3921	0	0
T30	109001	2281	0	0
T60	18220	0	0	0
T64	0	5674	0	0
T93	0	2799	0	0
T95	0	49277	0	0
T97	0	13996	0	0
T98	12239	0	0	0
T99	0	49821	0	0
T112	0	2445	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	28447321	0	0
T7	282026	0	0	0
T8	439723	0	0	0
T10	11230	3438	0	0
T11	67376	42002	0	0
T12	55042	48024	0	0
T13	11151	2341	0	0
T16	54747	46248	0	0
T29	61958	49994	0	0
T30	109001	98417	0	0
T38	0	74434	0	0
T93	0	77456	0	0
T94	0	43167	0	0
T98	12239	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T106,T67

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T6,T11
1	Covered	T12,T147,T65

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T23,T24,T25

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T72,T155
1	Covered	T72,T155

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T11

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T6,T11

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T6,T11
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T6,T11
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T11,T12

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T11,T12

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T4
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T6,T11
ReadWaitSt	252	Covered	T1,T6,T11
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T4
IdleSt->ReadSt	236	Covered	T1,T6,T11
InitSt->ErrorSt	315	Covered	T196,T190,T140
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T156,T157,T158
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T11,T7,T98
ReadSt->ReadWaitSt	252	Covered	T1,T6,T11
ReadWaitSt->ErrorSt	276	Covered	T146,T147,T197
ReadWaitSt->IdleSt	270	Covered	T1,T6,T11
ResetSt->ErrorSt	315	Covered	T71,T72,T73
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T11,T7,T98
CheckFailError	317	Covered	T72,T155
FsmStateError	289	Covered	T2,T3,T4
MacroEccCorrError	221	Covered	T6,T12,T106
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T9,T193,T146
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T11,T7,T98
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T72,T155
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T4
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T6,T106,T67
MacroEccCorrError->NoError	235	Covered	T12,T147,T65
NoError->AccessError	256	Covered	T11,T7,T98
NoError->CheckFailError	317	Covered	T72,T155
NoError->FsmStateError	289	Covered	T2,T3,T4
NoError->MacroEccCorrError	221	Covered	T6,T12,T106

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T6,T11

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T6,T11

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T6,T106,T67
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T156,T157,T158
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T6,T11
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T6,T11
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T93,T15,T112
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T11,T7,T98
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T12,T147,T65
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T6,T11
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T146,T147,T197
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T6,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T24,T25
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T72,T155
1	0	Covered	T72,T155
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	471208209	470337320	0	0
DigestKnown_A	471208209	470337320	0	0
DigestOffsetMustBeRepresentable_A	1150	1150	0	0
EccErrorState_A	471208209	6960	0	0
ErrorKnown_A	471208209	470337320	0	0
FsmStateKnown_A	471208209	470337320	0	0
InitDoneKnown_A	471208209	470337320	0	0
InitReadLocksPartition_A	471208209	93007450	0	0
InitWriteLocksPartition_A	471208209	93007450	0	0
OffsetMustBeBlockAligned_A	1150	1150	0	0
OtpAddrKnown_A	471208209	470337320	0	0
OtpCmdKnown_A	471208209	470337320	0	0
OtpErrorState_A	471208209	83	0	0
OtpReqKnown_A	471208209	470337320	0	0
OtpSizeKnown_A	471208209	470337320	0	0
OtpWdataKnown_A	471208209	470337320	0	0
ReadLockPropagation_A	471208209	197338059	0	0
SizeMustBeBlockAligned_A	1150	1150	0	0
TlulGntKnown_A	471208209	470337320	0	0
TlulRdataKnown_A	471208209	470337320	0	0
TlulReadOnReadLock_A	471208209	8663	0	0
TlulRerrorKnown_A	471208209	470337320	0	0
TlulRvalidKnown_A	471208209	470337320	0	0
WriteLockPropagation_A	471208209	2412056	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	471208209	27823913	0	0
u_state_regs_A	471208209	470337320	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	6960	0	0
T72	10861	3632	0	0
T74	8739	0	0	0
T96	90213	0	0	0
T132	61936	0	0	0
T150	36766	0	0	0
T155	0	3328	0	0
T156	8799	0	0	0
T160	66237	0	0	0
T161	20007	0	0	0
T162	35123	0	0	0
T163	19811	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	93007450	0	0
T1	11625	383	0	0
T2	38656	31203	0	0
T3	11965	1618	0	0
T4	88698	81867	0	0
T5	26615	971	0	0
T6	10710	4500	0	0
T10	11230	3241	0	0
T11	67376	3161	0	0
T12	55042	4558	0	0
T13	11151	3309	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	93007450	0	0
T1	11625	383	0	0
T2	38656	31203	0	0
T3	11965	1618	0	0
T4	88698	81867	0	0
T5	26615	971	0	0
T6	10710	4500	0	0
T10	11230	3241	0	0
T11	67376	3161	0	0
T12	55042	4558	0	0
T13	11151	3309	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	83	0	0
T14	92354	0	0	0
T35	12870	0	0	0
T52	12998	0	0	0
T103	30492	0	0	0
T146	459824	2	0	0
T147	60185	1	0	0
T148	100043	0	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T173	8219	0	0	0
T176	0	1	0	0
T177	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0
T181	0	1	0	0
T186	4188	0	0	0
T187	24047	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	197338059	0	0
T2	38656	31194	0	0
T3	11965	0	0	0
T4	88698	0	0	0
T5	26615	1173	0	0
T6	10710	0	0	0
T7	282026	218893	0	0
T8	0	119597	0	0
T10	11230	0	0	0
T11	67376	24838	0	0
T12	55042	2217	0	0
T13	11151	0	0	0
T16	0	8755	0	0
T29	0	4297	0	0
T30	0	19236	0	0
T98	0	3752	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	8663	0	0
T2	38656	14	0	0
T3	11965	2	0	0
T4	88698	29	0	0
T5	26615	0	0	0
T6	10710	0	0	0
T7	282026	14	0	0
T10	11230	0	0	0
T11	67376	3	0	0
T12	55042	1	0	0
T13	11151	0	0	0
T16	0	4	0	0
T29	0	1	0	0
T30	0	16	0	0
T98	0	4	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	2412056	0	0
T7	282026	0	0	0
T8	439723	0	0	0
T11	67376	9093	0	0
T12	55042	2795	0	0
T13	11151	0	0	0
T15	0	12142	0	0
T16	54747	3898	0	0
T29	61958	0	0	0
T30	109001	4909	0	0
T38	0	15852	0	0
T60	18220	0	0	0
T93	0	4476	0	0
T95	0	24414	0	0
T96	0	10311	0	0
T98	12239	0	0	0
T112	0	2141	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	27823913	0	0
T1	11625	3328	0	0
T2	38656	0	0	0
T3	11965	0	0	0
T4	88698	0	0	0
T5	26615	0	0	0
T6	10710	0	0	0
T10	11230	0	0	0
T11	67376	41917	0	0
T12	55042	47786	0	0
T13	11151	0	0	0
T16	0	46078	0	0
T30	0	98162	0	0
T38	0	74298	0	0
T93	0	77167	0	0
T94	0	43099	0	0
T98	0	3778	0	0
T193	0	3879	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T60,T66,T106

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T6,T11,T12
1	Covered	T12,T101,T147

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T23,T24,T25

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T153,T154
1	Covered	T153,T154

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T11,T12

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T11,T12

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00110110000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T6,T11,T12
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T6,T11,T12
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T4
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T6,T11
ReadWaitSt	252	Covered	T6,T11,T12
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T4
IdleSt->ReadSt	236	Covered	T1,T6,T11
InitSt->ErrorSt	315	Covered	T196,T190,T140
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T6,T13,T173
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T12,T7
ReadSt->ReadWaitSt	252	Covered	T6,T11,T12
ReadWaitSt->ErrorSt	276	Covered	T146,T182,T198
ReadWaitSt->IdleSt	270	Covered	T6,T11,T12
ResetSt->ErrorSt	315	Covered	T71,T72,T73
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T12,T7
CheckFailError	317	Covered	T153,T154
FsmStateError	289	Covered	T2,T3,T4
MacroEccCorrError	221	Covered	T12,T60,T101
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T8,T9,T193
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T12,T7
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T153,T154
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T4
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T60,T101,T66
MacroEccCorrError->NoError	235	Covered	T12,T44,T65
NoError->AccessError	256	Covered	T1,T12,T7
NoError->CheckFailError	317	Covered	T153,T154
NoError->FsmStateError	289	Covered	T2,T3,T4
NoError->MacroEccCorrError	221	Covered	T12,T60,T101

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T11,T12

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T11,T12

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T60,T66,T106
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T6,T13,T173
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T6,T11
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T6,T11,T12
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T8,T93,T102
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T12,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T12,T101,T147
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T6,T11,T12
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T146,T182,T198
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T6,T11,T12
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T24,T25
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T153,T154
1	0	Covered	T153,T154
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	471208209	470337320	0	0
DigestKnown_A	471208209	470337320	0	0
DigestOffsetMustBeRepresentable_A	1150	1150	0	0
EccErrorState_A	471208209	5035	0	0
ErrorKnown_A	471208209	470337320	0	0
FsmStateKnown_A	471208209	470337320	0	0
InitDoneKnown_A	471208209	470337320	0	0
InitReadLocksPartition_A	471208209	93191921	0	0
InitWriteLocksPartition_A	471208209	93191921	0	0
OffsetMustBeBlockAligned_A	1150	1150	0	0
OtpAddrKnown_A	471208209	470337320	0	0
OtpCmdKnown_A	471208209	470337320	0	0
OtpErrorState_A	471208209	47	0	0
OtpReqKnown_A	471208209	470337320	0	0
OtpSizeKnown_A	471208209	470337320	0	0
OtpWdataKnown_A	471208209	470337320	0	0
ReadLockPropagation_A	471208209	202182877	0	0
SizeMustBeBlockAligned_A	1150	1150	0	0
TlulGntKnown_A	471208209	470337320	0	0
TlulRdataKnown_A	471208209	470337320	0	0
TlulReadOnReadLock_A	471208209	8499	0	0
TlulRerrorKnown_A	471208209	470337320	0	0
TlulRvalidKnown_A	471208209	470337320	0	0
WriteLockPropagation_A	471208209	1554647	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	471208209	19722284	0	0
u_state_regs_A	471208209	470337320	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	5035	0	0
T153	8446	2082	0	0
T154	0	2953	0	0
T164	10496	0	0	0
T165	28873	0	0	0
T166	90811	0	0	0
T167	64353	0	0	0
T168	22828	0	0	0
T169	130681	0	0	0
T170	13842	0	0	0
T171	73621	0	0	0
T172	10937	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	93191921	0	0
T1	11625	417	0	0
T2	38656	31254	0	0
T3	11965	1669	0	0
T4	88698	81901	0	0
T5	26615	1022	0	0
T6	10710	4541	0	0
T10	11230	3292	0	0
T11	67376	3263	0	0
T12	55042	4813	0	0
T13	11151	3333	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	93191921	0	0
T1	11625	417	0	0
T2	38656	31254	0	0
T3	11965	1669	0	0
T4	88698	81901	0	0
T5	26615	1022	0	0
T6	10710	4541	0	0
T10	11230	3292	0	0
T11	67376	3263	0	0
T12	55042	4813	0	0
T13	11151	3333	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	47	0	0
T6	10710	1	0	0
T7	282026	0	0	0
T10	11230	0	0	0
T11	67376	0	0	0
T12	55042	0	0	0
T13	11151	1	0	0
T16	54747	0	0	0
T29	61958	0	0	0
T30	109001	0	0	0
T98	12239	0	0	0
T146	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T178	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	202182877	0	0
T1	11625	1587	0	0
T2	38656	31189	0	0
T3	11965	0	0	0
T4	88698	0	0	0
T5	26615	1161	0	0
T6	10710	0	0	0
T7	0	220107	0	0
T10	11230	0	0	0
T11	67376	24310	0	0
T12	55042	1080	0	0
T13	11151	0	0	0
T16	0	3013	0	0
T29	0	3897	0	0
T30	0	11911	0	0
T98	0	3891	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	8499	0	0
T1	11625	1	0	0
T2	38656	9	0	0
T3	11965	2	0	0
T4	88698	12	0	0
T5	26615	0	0	0
T6	10710	0	0	0
T7	0	13	0	0
T8	0	73	0	0
T10	11230	0	0	0
T11	67376	0	0	0
T12	55042	3	0	0
T13	11151	0	0	0
T16	0	7	0	0
T29	0	6	0	0
T30	0	8	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	1554647	0	0
T7	282026	0	0	0
T8	439723	0	0	0
T11	67376	18509	0	0
T12	55042	3148	0	0
T13	11151	0	0	0
T15	0	14546	0	0
T16	54747	0	0	0
T29	61958	0	0	0
T30	109001	10951	0	0
T44	0	5971	0	0
T60	18220	0	0	0
T64	0	5784	0	0
T94	0	30332	0	0
T95	0	52937	0	0
T98	12239	0	0	0
T99	0	26434	0	0
T190	0	4943	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	19722284	0	0
T1	11625	3311	0	0
T2	38656	0	0	0
T3	11965	0	0	0
T4	88698	0	0	0
T5	26615	6278	0	0
T6	10710	3446	0	0
T10	11230	3370	0	0
T11	67376	41832	0	0
T12	55042	47548	0	0
T13	11151	2319	0	0
T30	0	97907	0	0
T94	0	43031	0	0
T98	0	3761	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471208209	470337320	0	0
T1	11625	11467	0	0
T2	38656	38366	0	0
T3	11965	11755	0	0
T4	88698	88410	0	0
T5	26615	26391	0	0
T6	10710	10428	0	0
T10	11230	10994	0	0
T11	67376	66910	0	0
T12	55042	53835	0	0
T13	11151	10877	0	0