Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

28373760

1

T1

1376

T2

979

T3

7204

full_word

9238844

1

T1

260

T2

260

T3

6401

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	37612304	1			T1	1636		T2	1239		T3	13605
auto[TlIntgErrCmd]	105	1			T267	8		T268	4		T269	7
auto[TlIntgErrData]	95	1			T267	3		T268	2		T269	6
auto[TlIntgErrBoth]	100	1			T267	9		T268	4		T269	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10125751

1

T1

1337

T2

945

T3

11433

auto[1]

27486853

1

T1

299

T2

294

T3

2172

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6300785	1			T1	1189		T2	797		T3	6035
auto[TlIntgErrNone]	partial	auto[1]	22072700	1			T1	187		T2	182		T3	1169
auto[TlIntgErrNone]	full_word	auto[0]	3824844	1			T1	148		T2	148		T3	5398
auto[TlIntgErrNone]	full_word	auto[1]	5413975	1			T1	112		T2	112		T3	1003
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T267	2		T268	2		T269	2
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T267	5		T268	1		T269	5
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T267	1		T337	1		T343	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T268	1		T342	1		T338	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T267	1		T268	1		T269	3
auto[TlIntgErrData]	partial	auto[1]	42	1			T267	2		T268	1		T269	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T269	2		T271	1		T344	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T345	1		T342	1		T340	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1			T267	2		T268	2		T269	1
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T267	6		T268	2		T269	5
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T267	1		T269	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T340	1		T346	1		T347	2