Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.18		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	510768464	9412028	0	0
check_regwen_rd_A	510768464	2094	0	0
check_timeout_rd_A	510768464	1725	0	0
check_trigger_regwen_rd_A	510768464	2119	0	0
consistency_check_period_rd_A	510768464	2324	0	0
creator_sw_cfg_read_lock_rd_A	510768464	1776	0	0
direct_access_address_rd_A	510768464	1603	0	0
direct_access_wdata_0_rd_A	510768464	970	0	0
direct_access_wdata_1_rd_A	510768464	1194	0	0
integrity_check_period_rd_A	510768464	2354	0	0
intr_enable_rd_A	510768464	2832	0	0
owner_sw_cfg_read_lock_rd_A	510768464	1756	0	0
rot_creator_auth_codesign_read_lock_rd_A	510768464	1687	0	0
rot_creator_auth_state_read_lock_rd_A	510768464	1609	0	0
vendor_test_read_lock_rd_A	510768464	1744	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510768464	9412028	0	0
T7	158227	277120	0	0
T13	602187	153238	0	0
T14	211716	41040	0	0
T17	0	67703	0	0
T37	0	140483	0	0
T69	100576	0	0	0
T103	4818	0	0	0
T104	16330	0	0	0
T109	21108	0	0	0
T119	10187	0	0	0
T132	0	196755	0	0
T135	0	278837	0	0
T204	85797	0	0	0
T237	0	32642	0	0
T255	0	31706	0	0
T274	0	115864	0	0
T275	11947	0	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510768464	2094	0	0
T18	445906	0	0	0
T138	609163	0	0	0
T146	121644	0	0	0
T151	943213	0	0	0
T190	13949	0	0	0
T255	162456	23	0	0
T256	0	80	0	0
T259	39268	0	0	0
T277	0	203	0	0
T278	0	70	0	0
T310	0	59	0	0
T312	0	70	0	0
T313	0	43	0	0
T314	0	70	0	0
T315	0	73	0	0
T316	0	24	0	0
T317	43765	0	0	0
T318	15991	0	0	0
T319	72496	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510768464	1725	0	0
T18	445906	0	0	0
T138	609163	0	0	0
T146	121644	0	0	0
T151	943213	0	0	0
T190	13949	0	0	0
T255	162456	49	0	0
T256	0	82	0	0
T259	39268	0	0	0
T277	0	135	0	0
T278	0	48	0	0
T310	0	75	0	0
T312	0	71	0	0
T313	0	26	0	0
T314	0	98	0	0
T315	0	89	0	0
T316	0	50	0	0
T317	43765	0	0	0
T318	15991	0	0	0
T319	72496	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510768464	2119	0	0
T18	445906	0	0	0
T138	609163	0	0	0
T146	121644	0	0	0
T151	943213	0	0	0
T190	13949	0	0	0
T255	162456	57	0	0
T256	0	67	0	0
T259	39268	0	0	0
T277	0	166	0	0
T278	0	73	0	0
T310	0	61	0	0
T312	0	70	0	0
T313	0	16	0	0
T314	0	104	0	0
T315	0	86	0	0
T316	0	33	0	0
T317	43765	0	0	0
T318	15991	0	0	0
T319	72496	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510768464	2324	0	0
T18	445906	0	0	0
T138	609163	0	0	0
T146	121644	0	0	0
T151	943213	0	0	0
T190	13949	0	0	0
T255	162456	63	0	0
T256	0	134	0	0
T259	39268	0	0	0
T277	0	198	0	0
T278	0	83	0	0
T310	0	71	0	0
T312	0	105	0	0
T313	0	40	0	0
T314	0	67	0	0
T315	0	88	0	0
T316	0	30	0	0
T317	43765	0	0	0
T318	15991	0	0	0
T319	72496	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510768464	1776	0	0
T18	445906	0	0	0
T138	609163	0	0	0
T146	121644	0	0	0
T151	943213	0	0	0
T190	13949	0	0	0
T255	162456	65	0	0
T256	0	115	0	0
T259	39268	0	0	0
T277	0	135	0	0
T278	0	68	0	0
T310	0	76	0	0
T312	0	94	0	0
T313	0	30	0	0
T314	0	78	0	0
T315	0	108	0	0
T316	0	31	0	0
T317	43765	0	0	0
T318	15991	0	0	0
T319	72496	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510768464	1603	0	0
T18	445906	0	0	0
T138	609163	0	0	0
T146	121644	0	0	0
T151	943213	0	0	0
T190	13949	0	0	0
T255	162456	51	0	0
T256	0	135	0	0
T259	39268	0	0	0
T277	0	138	0	0
T278	0	28	0	0
T310	0	115	0	0
T312	0	98	0	0
T313	0	31	0	0
T314	0	101	0	0
T315	0	67	0	0
T316	0	12	0	0
T317	43765	0	0	0
T318	15991	0	0	0
T319	72496	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510768464	970	0	0
T18	445906	0	0	0
T138	609163	0	0	0
T146	121644	0	0	0
T151	943213	0	0	0
T190	13949	0	0	0
T255	162456	33	0	0
T256	0	37	0	0
T259	39268	0	0	0
T277	0	165	0	0
T278	0	41	0	0
T310	0	51	0	0
T312	0	44	0	0
T313	0	27	0	0
T314	0	46	0	0
T315	0	33	0	0
T316	0	38	0	0
T317	43765	0	0	0
T318	15991	0	0	0
T319	72496	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510768464	1194	0	0
T18	445906	0	0	0
T138	609163	0	0	0
T146	121644	0	0	0
T151	943213	0	0	0
T190	13949	0	0	0
T227	0	38	0	0
T255	162456	42	0	0
T256	0	124	0	0
T259	39268	0	0	0
T277	0	162	0	0
T278	0	97	0	0
T310	0	38	0	0
T312	0	80	0	0
T314	0	57	0	0
T315	0	97	0	0
T316	0	4	0	0
T317	43765	0	0	0
T318	15991	0	0	0
T319	72496	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510768464	2354	0	0
T18	445906	0	0	0
T138	609163	0	0	0
T146	121644	0	0	0
T151	943213	0	0	0
T190	13949	0	0	0
T255	162456	49	0	0
T256	0	130	0	0
T259	39268	0	0	0
T277	0	116	0	0
T278	0	83	0	0
T310	0	76	0	0
T312	0	89	0	0
T313	0	29	0	0
T314	0	77	0	0
T315	0	71	0	0
T316	0	32	0	0
T317	43765	0	0	0
T318	15991	0	0	0
T319	72496	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510768464	2832	0	0
T99	194503	58	0	0
T188	9246	0	0	0
T189	498946	0	0	0
T237	201333	0	0	0
T255	0	38	0	0
T256	0	98	0	0
T274	519656	0	0	0
T277	0	150	0	0
T278	0	44	0	0
T310	0	94	0	0
T312	0	51	0	0
T313	0	25	0	0
T314	0	91	0	0
T320	0	45	0	0
T321	11502	0	0	0
T322	64047	0	0	0
T323	20392	0	0	0
T324	8916	0	0	0
T325	16046	0	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510768464	1756	0	0
T18	445906	0	0	0
T138	609163	0	0	0
T146	121644	0	0	0
T151	943213	0	0	0
T190	13949	0	0	0
T255	162456	52	0	0
T256	0	106	0	0
T259	39268	0	0	0
T277	0	112	0	0
T278	0	70	0	0
T310	0	70	0	0
T312	0	103	0	0
T313	0	36	0	0
T314	0	108	0	0
T315	0	95	0	0
T316	0	28	0	0
T317	43765	0	0	0
T318	15991	0	0	0
T319	72496	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510768464	1687	0	0
T18	445906	0	0	0
T138	609163	0	0	0
T146	121644	0	0	0
T151	943213	0	0	0
T190	13949	0	0	0
T255	162456	61	0	0
T256	0	94	0	0
T259	39268	0	0	0
T277	0	170	0	0
T278	0	69	0	0
T310	0	53	0	0
T312	0	81	0	0
T313	0	18	0	0
T314	0	102	0	0
T315	0	85	0	0
T316	0	46	0	0
T317	43765	0	0	0
T318	15991	0	0	0
T319	72496	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510768464	1609	0	0
T18	445906	0	0	0
T138	609163	0	0	0
T146	121644	0	0	0
T151	943213	0	0	0
T190	13949	0	0	0
T255	162456	58	0	0
T256	0	91	0	0
T259	39268	0	0	0
T277	0	120	0	0
T278	0	41	0	0
T310	0	76	0	0
T312	0	86	0	0
T313	0	31	0	0
T314	0	83	0	0
T315	0	79	0	0
T316	0	30	0	0
T317	43765	0	0	0
T318	15991	0	0	0
T319	72496	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510768464	1744	0	0
T18	445906	0	0	0
T138	609163	0	0	0
T146	121644	0	0	0
T151	943213	0	0	0
T190	13949	0	0	0
T255	162456	70	0	0
T256	0	125	0	0
T259	39268	0	0	0
T277	0	188	0	0
T278	0	67	0	0
T310	0	99	0	0
T312	0	79	0	0
T313	0	9	0	0
T314	0	57	0	0
T315	0	121	0	0
T316	0	14	0	0
T317	43765	0	0	0
T318	15991	0	0	0
T319	72496	0	0	0