Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.23	100.00	100.00		90.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.56	100.00	100.00	100.00	90.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.18		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.18		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.75	100.00	97.06		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.83	100.00	97.06	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.18		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T4
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T23,T24,T25

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T153,T163,T164
1	Covered	T153,T163,T164

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T8
1	1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T12

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T12

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	11	84.62
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T4
ReadWaitSt	252	Covered	T1,T2,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T3
IdleSt->ReadSt	236	Covered	T1,T2,T4
InitSt->ErrorSt	315	Covered	T206
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T199,T207,T208
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T4,T8,T5
ReadSt->ReadWaitSt	252	Covered	T1,T2,T4
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T1,T2,T4
ResetSt->ErrorSt	315	Covered	T67,T68,T20
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T4,T8,T5
CheckFailError	317	Covered	T153,T163,T164
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T8,T5,T102
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T4,T8,T5
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T153,T163,T164
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T4,T8,T5
NoError->CheckFailError	317	Covered	T153,T163,T164
NoError->FsmStateError	289	Covered	T1,T2,T3
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T5,T6,T131
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T4,T8,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T24,T25
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T4,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T4,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T153,T163,T164
1	0	Covered	T153,T163,T164
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	507520713	506662512	0	0
DigestKnown_A	507520713	506662512	0	0
DigestOffsetMustBeRepresentable_A	1153	1153	0	0
EccErrorState_A	507520713	9872	0	0
ErrorKnown_A	507520713	506662512	0	0
FsmStateKnown_A	507520713	506662512	0	0
InitDoneKnown_A	507520713	506662512	0	0
InitReadLocksPartition_A	507520713	101732463	0	0
InitWriteLocksPartition_A	507520713	101732463	0	0
OffsetMustBeBlockAligned_A	1153	1153	0	0
OtpAddrKnown_A	507520713	506662512	0	0
OtpCmdKnown_A	507520713	506662512	0	0
OtpErrorState_A	507520713	0	0	0
OtpReqKnown_A	507520713	506662512	0	0
OtpSizeKnown_A	507520713	506662512	0	0
OtpWdataKnown_A	507520713	506662512	0	0
ReadLockPropagation_A	507520713	228772275	0	0
SizeMustBeBlockAligned_A	1153	1153	0	0
TlulGntKnown_A	507520713	506662512	0	0
TlulRdataKnown_A	507520713	506662512	0	0
TlulReadOnReadLock_A	507520713	8030	0	0
TlulRerrorKnown_A	507520713	506662512	0	0
TlulRvalidKnown_A	507520713	506662512	0	0
WriteLockPropagation_A	507520713	3044015	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	507520713	32582298	0	0
u_state_regs_A	507520713	506662512	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1153	1153	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	9872	0	0
T122	11487	0	0	0
T153	10547	3503	0	0
T163	0	2427	0	0
T164	0	3942	0	0
T172	45573	0	0	0
T173	443623	0	0	0
T174	99346	0	0	0
T175	33614	0	0	0
T176	12087	0	0	0
T177	25066	0	0	0
T178	106520	0	0	0
T179	25708	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	101732463	0	0
T1	14461	5384	0	0
T2	10443	4256	0	0
T3	131883	113841	0	0
T4	88237	6145	0	0
T5	310233	21092	0	0
T8	26183	8566	0	0
T9	20684	14542	0	0
T10	13849	3513	0	0
T11	49859	44142	0	0
T12	14307	4781	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	101732463	0	0
T1	14461	5384	0	0
T2	10443	4256	0	0
T3	131883	113841	0	0
T4	88237	6145	0	0
T5	310233	21092	0	0
T8	26183	8566	0	0
T9	20684	14542	0	0
T10	13849	3513	0	0
T11	49859	44142	0	0
T12	14307	4781	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1153	1153	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	228772275	0	0
T3	131883	123418	0	0
T4	88237	13742	0	0
T5	310233	45282	0	0
T6	78506	7553	0	0
T7	0	666669	0	0
T8	26183	15830	0	0
T9	20684	0	0	0
T10	13849	0	0	0
T11	49859	0	0	0
T12	14307	0	0	0
T13	0	308697	0	0
T14	0	147816	0	0
T16	75185	17295	0	0
T102	0	19456	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1153	1153	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	8030	0	0
T3	131883	18	0	0
T4	88237	10	0	0
T5	310233	53	0	0
T6	78506	11	0	0
T8	26183	5	0	0
T9	20684	3	0	0
T10	13849	0	0	0
T11	49859	9	0	0
T12	14307	0	0	0
T16	75185	14	0	0
T101	0	8	0	0
T102	0	24	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	3044015	0	0
T4	88237	5176	0	0
T5	310233	2805	0	0
T6	78506	0	0	0
T8	26183	0	0	0
T9	20684	0	0	0
T10	13849	0	0	0
T11	49859	0	0	0
T12	14307	0	0	0
T16	75185	5557	0	0
T61	12051	0	0	0
T93	0	9308	0	0
T94	0	6146	0	0
T95	0	10721	0	0
T105	0	734	0	0
T107	0	4158	0	0
T112	0	4707	0	0
T131	0	3650	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	32582298	0	0
T4	88237	77029	0	0
T5	310233	196233	0	0
T6	78506	64992	0	0
T8	26183	0	0	0
T9	20684	0	0	0
T10	13849	0	0	0
T11	49859	0	0	0
T12	14307	3698	0	0
T16	75185	64499	0	0
T61	12051	0	0	0
T69	0	84480	0	0
T102	0	3100	0	0
T110	0	6806	0	0
T119	0	3727	0	0
T204	0	3353	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T26,T27

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T69,T155

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T23,T24,T25

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T67,T153
1	Covered	T67,T153

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T8
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T3
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T199,T207,T208
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T61,T119,T180
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T3,T4,T8
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T165,T189,T191
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T67,T68,T20
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T3,T4,T8
CheckFailError	317	Covered	T67,T153
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Covered	T4,T12,T69
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T3,T8,T102
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T3,T4,T8
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T67,T153
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T12,T155,T26
MacroEccCorrError->NoError	235	Covered	T4,T69,T51
NoError->AccessError	256	Covered	T3,T4,T8
NoError->CheckFailError	317	Covered	T67,T153
NoError->FsmStateError	289	Covered	T1,T2,T4
NoError->MacroEccCorrError	221	Covered	T4,T12,T69

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T12,T26,T27
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T61,T119,T180
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T5,T6,T7
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T4,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T4,T69,T155
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T165,T189,T191
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T24,T25
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T4,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T4,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T67,T153
1	0	Covered	T67,T153
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	507520713	506662512	0	0
DigestKnown_A	507520713	506662512	0	0
DigestOffsetMustBeRepresentable_A	1153	1153	0	0
EccErrorState_A	507520713	7045	0	0
ErrorKnown_A	507520713	506662512	0	0
FsmStateKnown_A	507520713	506662512	0	0
InitDoneKnown_A	507520713	506662512	0	0
InitReadLocksPartition_A	507520713	101913919	0	0
InitWriteLocksPartition_A	507520713	101913919	0	0
OffsetMustBeBlockAligned_A	1153	1153	0	0
OtpAddrKnown_A	507520713	506662512	0	0
OtpCmdKnown_A	507520713	506662512	0	0
OtpErrorState_A	507520713	66	0	0
OtpReqKnown_A	507520713	506662512	0	0
OtpSizeKnown_A	507520713	506662512	0	0
OtpWdataKnown_A	507520713	506662512	0	0
ReadLockPropagation_A	507520713	223823790	0	0
SizeMustBeBlockAligned_A	1153	1153	0	0
TlulGntKnown_A	507520713	506662512	0	0
TlulRdataKnown_A	507520713	506662512	0	0
TlulReadOnReadLock_A	507520713	7976	0	0
TlulRerrorKnown_A	507520713	506662512	0	0
TlulRvalidKnown_A	507520713	506662512	0	0
WriteLockPropagation_A	507520713	2702811	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	507520713	31902126	0	0
u_state_regs_A	507520713	506662512	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1153	1153	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	7045	0	0
T28	13636	0	0	0
T67	18593	3542	0	0
T95	102744	0	0	0
T96	38542	0	0	0
T108	63773	0	0	0
T153	0	3503	0	0
T162	16986	0	0	0
T168	12028	0	0	0
T169	14984	0	0	0
T170	4792	0	0	0
T171	4870	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	101913919	0	0
T1	14461	5435	0	0
T2	10443	4307	0	0
T3	131883	113875	0	0
T4	88237	6400	0	0
T5	310233	22302	0	0
T8	26183	8617	0	0
T9	20684	14610	0	0
T10	13849	3547	0	0
T11	49859	44176	0	0
T12	14307	4832	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	101913919	0	0
T1	14461	5435	0	0
T2	10443	4307	0	0
T3	131883	113875	0	0
T4	88237	6400	0	0
T5	310233	22302	0	0
T8	26183	8617	0	0
T9	20684	14610	0	0
T10	13849	3547	0	0
T11	49859	44176	0	0
T12	14307	4832	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1153	1153	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	66	0	0
T7	158227	0	0	0
T13	602187	0	0	0
T14	211716	0	0	0
T61	12051	1	0	0
T101	36316	0	0	0
T102	26254	0	0	0
T103	4818	0	0	0
T104	16330	0	0	0
T109	21108	0	0	0
T119	10187	1	0	0
T165	0	1	0	0
T180	0	1	0	0
T182	0	1	0	0
T185	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	223823790	0	0
T3	131883	117313	0	0
T4	88237	12571	0	0
T5	310233	28842	0	0
T6	78506	10043	0	0
T7	0	666736	0	0
T8	26183	15816	0	0
T9	20684	0	0	0
T10	13849	0	0	0
T11	49859	0	0	0
T12	14307	0	0	0
T13	0	301419	0	0
T14	0	557287	0	0
T16	75185	13250	0	0
T102	0	19223	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1153	1153	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	7976	0	0
T3	131883	13	0	0
T4	88237	12	0	0
T5	310233	38	0	0
T6	78506	18	0	0
T8	26183	6	0	0
T9	20684	5	0	0
T10	13849	0	0	0
T11	49859	13	0	0
T12	14307	0	0	0
T16	75185	10	0	0
T101	0	5	0	0
T102	0	14	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	2702811	0	0
T4	88237	7769	0	0
T5	310233	12271	0	0
T6	78506	958	0	0
T8	26183	0	0	0
T9	20684	0	0	0
T10	13849	0	0	0
T11	49859	0	0	0
T12	14307	0	0	0
T16	75185	11019	0	0
T61	12051	0	0	0
T69	0	10045	0	0
T93	0	3345	0	0
T94	0	4691	0	0
T107	0	4919	0	0
T112	0	2316	0	0
T131	0	2192	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	31902126	0	0
T4	88237	76808	0	0
T5	310233	210013	0	0
T6	78506	64720	0	0
T8	26183	0	0	0
T9	20684	0	0	0
T10	13849	0	0	0
T11	49859	0	0	0
T12	14307	0	0	0
T16	75185	64312	0	0
T61	12051	3629	0	0
T69	0	84327	0	0
T102	0	3066	0	0
T110	0	6772	0	0
T119	0	3722	0	0
T204	0	3319	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T41,T27,T63

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T101,T69

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T23,T24,T25

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T67,T163,T164
1	Covered	T67,T163,T164

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T8
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00110110000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T5

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T5

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T3
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T199,T207,T208
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T12,T61,T119
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T3,T4,T8
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T101,T191,T192
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T67,T68,T20
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T3,T4,T8
CheckFailError	317	Covered	T67,T163,T164
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Covered	T4,T101,T69
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T3,T8,T13
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T3,T4,T8
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T67,T163,T164
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T101,T41,T27
MacroEccCorrError->NoError	235	Covered	T4,T69,T51
NoError->AccessError	256	Covered	T3,T4,T8
NoError->CheckFailError	317	Covered	T67,T163,T164
NoError->FsmStateError	289	Covered	T1,T2,T4
NoError->MacroEccCorrError	221	Covered	T4,T101,T69

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T41,T27,T63
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T12,T183,T184
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T5,T6,T7
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T4,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T4,T101,T69
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T101,T191,T192
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T24,T25
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T4,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T4,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T67,T163,T164
1	0	Covered	T67,T163,T164
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	507520713	506662512	0	0
DigestKnown_A	507520713	506662512	0	0
DigestOffsetMustBeRepresentable_A	1153	1153	0	0
EccErrorState_A	507520713	9911	0	0
ErrorKnown_A	507520713	506662512	0	0
FsmStateKnown_A	507520713	506662512	0	0
InitDoneKnown_A	507520713	506662512	0	0
InitReadLocksPartition_A	507520713	102094151	0	0
InitWriteLocksPartition_A	507520713	102094151	0	0
OffsetMustBeBlockAligned_A	1153	1153	0	0
OtpAddrKnown_A	507520713	506662512	0	0
OtpCmdKnown_A	507520713	506662512	0	0
OtpErrorState_A	507520713	61	0	0
OtpReqKnown_A	507520713	506662512	0	0
OtpSizeKnown_A	507520713	506662512	0	0
OtpWdataKnown_A	507520713	506662512	0	0
ReadLockPropagation_A	507520713	224377301	0	0
SizeMustBeBlockAligned_A	1153	1153	0	0
TlulGntKnown_A	507520713	506662512	0	0
TlulRdataKnown_A	507520713	506662512	0	0
TlulReadOnReadLock_A	507520713	8463	0	0
TlulRerrorKnown_A	507520713	506662512	0	0
TlulRvalidKnown_A	507520713	506662512	0	0
WriteLockPropagation_A	507520713	2300673	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	507520713	20326892	0	0
u_state_regs_A	507520713	506662512	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1153	1153	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	9911	0	0
T28	13636	0	0	0
T67	18593	3542	0	0
T95	102744	0	0	0
T96	38542	0	0	0
T108	63773	0	0	0
T162	16986	0	0	0
T163	0	2427	0	0
T164	0	3942	0	0
T168	12028	0	0	0
T169	14984	0	0	0
T170	4792	0	0	0
T171	4870	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	102094151	0	0
T1	14461	5486	0	0
T2	10443	4358	0	0
T3	131883	113909	0	0
T4	88237	6655	0	0
T5	310233	23509	0	0
T8	26183	8668	0	0
T9	20684	14678	0	0
T10	13849	3581	0	0
T11	49859	44210	0	0
T12	14307	4873	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	102094151	0	0
T1	14461	5486	0	0
T2	10443	4358	0	0
T3	131883	113909	0	0
T4	88237	6655	0	0
T5	310233	23509	0	0
T8	26183	8668	0	0
T9	20684	14678	0	0
T10	13849	3581	0	0
T11	49859	44210	0	0
T12	14307	4873	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1153	1153	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	61	0	0
T6	78506	0	0	0
T7	158227	0	0	0
T12	14307	1	0	0
T13	602187	0	0	0
T14	211716	0	0	0
T16	75185	0	0	0
T61	12051	0	0	0
T101	36316	1	0	0
T102	26254	0	0	0
T103	4818	0	0	0
T183	0	1	0	0
T184	0	1	0	0
T186	0	1	0	0
T191	0	1	0	0
T192	0	1	0	0
T193	0	2	0	0
T194	0	1	0	0
T195	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	224377301	0	0
T3	131883	117298	0	0
T4	88237	10050	0	0
T5	310233	32857	0	0
T6	78506	10692	0	0
T7	0	667486	0	0
T8	26183	15803	0	0
T9	20684	0	0	0
T10	13849	0	0	0
T11	49859	0	0	0
T12	14307	0	0	0
T13	0	308637	0	0
T14	0	558290	0	0
T16	75185	14614	0	0
T69	0	44507	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1153	1153	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	8463	0	0
T3	131883	16	0	0
T4	88237	8	0	0
T5	310233	44	0	0
T6	78506	13	0	0
T8	26183	6	0	0
T9	20684	4	0	0
T10	13849	0	0	0
T11	49859	12	0	0
T12	14307	0	0	0
T16	75185	14	0	0
T101	0	3	0	0
T102	0	16	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	2300673	0	0
T5	310233	11486	0	0
T6	78506	6612	0	0
T9	20684	0	0	0
T10	13849	0	0	0
T11	49859	0	0	0
T12	14307	0	0	0
T16	75185	3241	0	0
T61	12051	0	0	0
T69	0	12921	0	0
T93	0	3147	0	0
T94	0	10770	0	0
T96	0	1208	0	0
T101	36316	0	0	0
T102	26254	0	0	0
T107	0	846	0	0
T131	0	2869	0	0
T133	0	7316	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	20326892	0	0
T4	88237	76587	0	0
T5	310233	149570	0	0
T6	78506	64448	0	0
T8	26183	4805	0	0
T9	20684	0	0	0
T10	13849	0	0	0
T11	49859	0	0	0
T12	14307	3676	0	0
T16	75185	64125	0	0
T61	12051	0	0	0
T69	0	84174	0	0
T102	0	3032	0	0
T110	0	6738	0	0
T204	0	3285	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507520713	506662512	0	0
T1	14461	14157	0	0
T2	10443	10198	0	0
T3	131883	131688	0	0
T4	88237	86935	0	0
T5	310233	304336	0	0
T8	26183	25908	0	0
T9	20684	20437	0	0
T10	13849	13570	0	0
T11	49859	49712	0	0
T12	14307	14037	0	0