Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_buf_err_code_cg_wrap::buf_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_buf_err_code_cg_wrap::buf_err_code_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
83.33	69.44	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

6 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
buf_err_code_cg_wrap[OtpSecret0ErrIdx]	0.00	1	100	1	64	64
buf_err_code_cg_wrap[OtpHwCfg0ErrIdx]	83.33	1	100	1	64	64
buf_err_code_cg_wrap[OtpHwCfg1ErrIdx]	83.33	1	100	1	64	64
buf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]	83.33	1	100	1	64	64
buf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]	83.33	1	100	1	64	64
buf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]	83.33	1	100	1	64	64

---

Group Instance : buf_err_code_cg_wrap[OtpSecret0ErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[OtpSecret0ErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	6	0	0.00

Variables for Group Instance buf_err_code_cg_wrap[OtpSecret0ErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	6	6	0	0.00	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[OtpHwCfg0ErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[OtpHwCfg0ErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	1	5	83.33

Variables for Group Instance buf_err_code_cg_wrap[OtpHwCfg0ErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	6	1	5	83.33	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[OtpHwCfg1ErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[OtpHwCfg1ErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	1	5	83.33

Variables for Group Instance buf_err_code_cg_wrap[OtpHwCfg1ErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	6	1	5	83.33	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	1	5	83.33

Variables for Group Instance buf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	6	1	5	83.33	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	1	5	83.33

Variables for Group Instance buf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	6	1	5	83.33	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	1	5	83.33

Variables for Group Instance buf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	6	1	5	83.33	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	6	0	0.00

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
fsm_err	0	1	1
check_fail	0	1	1
ecc_uncorr_err	0	1	1
ecc_corr_err	0	1	1
macro_err	0	1	1
no_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	1	5	83.33

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	116377	1			T1	1		T2	46		T4	1
check_fail	3	1			T62	1		T63	1		T64	1
ecc_uncorr_err	78	1			T74	1		T26	1		T49	1
ecc_corr_err	277	1			T50	51		T60	44		T61	53
no_err	157737	1			T2	135		T3	90		T6	237

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	1	5	83.33

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	116356	1			T2	46		T10	1		T13	16
check_fail	6	1			T35	1		T36	1		T37	1
ecc_uncorr_err	94	1			T75	78		T25	1		T47	1
ecc_corr_err	316	1			T33	46		T27	41		T34	22
no_err	157606	1			T2	135		T3	90		T6	237

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	1	5	83.33

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	116226	1			T1	1		T2	46		T13	16
check_fail	13	1			T29	1		T30	1		T31	1
ecc_uncorr_err	209	1			T33	49		T78	1		T48	1
ecc_corr_err	88	1			T27	42		T28	46		-	-
no_err	158172	1			T2	135		T3	93		T6	237

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	1	5	83.33

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	116216	1			T1	1		T2	46		T4	1
check_fail	32	1			T43	1		T44	1		T45	1
ecc_uncorr_err	178	1			T46	1		T79	1		T105	1
ecc_corr_err	145	1			T33	43		T41	63		T42	39
no_err	158024	1			T2	135		T3	93		T6	237

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	1	5	83.33

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	116236	1			T1	1		T2	46		T4	1
check_fail	21	1			T53	1		T54	1		T55	1
ecc_uncorr_err	183	1			T66	1		T77	28		T111	1
ecc_corr_err	333	1			T50	52		T51	72		T52	36
no_err	157760	1			T2	135		T3	92		T6	237