Unified Coverage Report :: Module :: prim_mubi8_sender

Module : prim_mubi8_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_bufs[0].u_prim_mubi8_sender_write_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[1].u_prim_mubi8_sender_write_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[2].u_prim_mubi8_sender_write_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[3].u_prim_mubi8_sender_write_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[4].u_prim_mubi8_sender_write_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[5].u_prim_mubi8_sender_write_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[5].u_prim_mubi8_sender_read_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[6].u_prim_mubi8_sender_write_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[6].u_prim_mubi8_sender_read_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[7].u_prim_mubi8_sender_write_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[7].u_prim_mubi8_sender_read_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[8].u_prim_mubi8_sender_write_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[8].u_prim_mubi8_sender_read_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[10].u_prim_mubi8_sender_write_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[10].u_prim_mubi8_sender_read_lock	83.33	50.00				100.00	100.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_write_lock_pre	83.33	50.00				100.00	100.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_read_lock_pre	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[0].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
tb.dut.gen_bufs[1].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
tb.dut.gen_bufs[2].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
tb.dut.gen_bufs[3].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
tb.dut.gen_bufs[4].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
tb.dut.gen_bufs[9].u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
tb.dut.gen_bufs[9].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[8].u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[8].u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[10].u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[10].u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_write_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	96.91	100.00		90.48	100.00	82.35	gen_partitions[10].gen_lifecycle.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_read_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	96.91	100.00		90.48	100.00	82.35	gen_partitions[10].gen_lifecycle.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_bufs[9].u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_bufs[9].u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.23	100.00	100.00		90.00	100.00	96.15	gen_partitions[0].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.23	100.00	100.00		90.00	100.00	96.15	gen_partitions[0].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.23	100.00	100.00		90.00	100.00	96.15	gen_partitions[0].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	100.00		91.67	100.00	100.00	gen_partitions[1].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	100.00		91.67	100.00	100.00	gen_partitions[1].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	100.00		91.67	100.00	100.00	gen_partitions[1].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.75	100.00	97.06		91.67	100.00	100.00	gen_partitions[2].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.75	100.00	97.06		91.67	100.00	100.00	gen_partitions[2].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.75	100.00	97.06		91.67	100.00	100.00	gen_partitions[2].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	100.00		91.67	100.00	100.00	gen_partitions[3].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	100.00		91.67	100.00	100.00	gen_partitions[3].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	100.00		91.67	100.00	100.00	gen_partitions[3].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	100.00		91.67	100.00	100.00	gen_partitions[4].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	100.00		91.67	100.00	100.00	gen_partitions[4].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	100.00		91.67	100.00	100.00	gen_partitions[4].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.82	97.64	95.24		92.00	96.36	82.86	gen_partitions[5].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.82	97.64	95.24		92.00	96.36	82.86	gen_partitions[5].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.82	97.64	95.24		92.00	96.36	82.86	gen_partitions[5].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.75	95.45	92.86		91.67	90.91	82.86	gen_partitions[6].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.75	95.45	92.86		91.67	90.91	82.86	gen_partitions[6].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.75	95.45	92.86		91.67	90.91	82.86	gen_partitions[6].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.65	98.00	93.75		91.67	95.38	94.44	gen_partitions[7].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.65	98.00	93.75		91.67	95.38	94.44	gen_partitions[7].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.65	98.00	93.75		91.67	95.38	94.44	gen_partitions[7].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.65	98.00	93.75		91.67	95.38	94.44	gen_partitions[7].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.24	97.33	91.67		88.89	93.85	94.44	gen_partitions[8].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.24	97.33	91.67		88.89	93.85	94.44	gen_partitions[8].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.24	97.33	91.67		88.89	93.85	94.44	gen_partitions[8].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.24	97.33	91.67		88.89	93.85	94.44	gen_partitions[8].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.65	98.00	93.75		91.67	95.38	94.44	gen_partitions[9].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.65	98.00	93.75		91.67	95.38	94.44	gen_partitions[9].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.65	98.00	93.75		91.67	95.38	94.44	gen_partitions[9].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.65	98.00	93.75		91.67	95.38	94.44	gen_partitions[9].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

Line Coverage for Module : prim_mubi8_sender

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Module : prim_mubi8_sender

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_mubi8_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	896040	879168	0	0
T2	1845774	1830840	0	0
T3	4392249	4320258	0	0
T4	650142	634125	0	0
T5	266703	263739	0	0
T6	3741651	3692004	0	0
T10	572280	555009	0	0
T11	344280	341088	0	0
T12	622098	610413	0	0
T13	560424	545604	0	0

Line Coverage for Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	0	1
48	0	1
55	1	1
56	1	1
58	1	1
85	0	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	0	1
48	0	1
55	1	1
56	1	1
58	1	1
85	0	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	0	1
48	0	1
55	1	1
56	1	1
58	1	1
85	0	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	0	1
48	0	1
55	1	1
56	1	1
58	1	1
85	0	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	0	1
48	0	1
55	1	1
56	1	1
58	1	1
85	0	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	0	1
48	0	1
55	1	1
56	1	1
58	1	1
85	0	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	0	1
48	0	1
55	1	1
56	1	1
58	1	1
85	0	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	0	1
48	0	1
55	1	1
56	1	1
58	1	1
85	0	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	0	1
48	0	1
55	1	1
56	1	1
58	1	1
85	0	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	0	1
48	0	1
55	1	1
56	1	1
58	1	1
85	0	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	0	1
48	0	1
55	1	1
56	1	1
58	1	1
85	0	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_bufs[8].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	0	1
48	0	1
55	1	1
56	1	1
58	1	1
85	0	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[8].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[8].u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_bufs[8].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	0	1
48	0	1
55	1	1
56	1	1
58	1	1
85	0	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[8].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[8].u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_bufs[10].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	0	1
48	0	1
55	1	1
56	1	1
58	1	1
85	0	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[10].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[10].u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_bufs[10].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	0	1
48	0	1
55	1	1
56	1	1
58	1	1
85	0	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[10].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[10].u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	0	1
48	0	1
55	1	1
56	1	1
58	1	1
85	0	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	0	1
48	0	1
55	1	1
56	1	1
58	1	1
85	0	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_bufs[9].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[9].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[9].u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_bufs[9].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[9].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[9].u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	485267964	484436711	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0