Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

27470012

1

T1

136719

T2

34

T3

2571

full_word

8866794

1

T1

41424

T2

6

T3

2332

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	36336506	1			T1	178143		T2	40		T3	4903
auto[TlIntgErrCmd]	102	1			T272	6		T273	8		T274	8
auto[TlIntgErrData]	120	1			T272	8		T273	9		T274	6
auto[TlIntgErrBoth]	78	1			T272	6		T273	3		T274	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9875473

1

T1

37199

T2

1

T3

4425

auto[1]

26461333

1

T1

140944

T2

39

T3

478

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6192921	1			T1	23601		T2	1		T3	2290
auto[TlIntgErrNone]	partial	auto[1]	21276814	1			T1	113118		T2	33		T3	281
auto[TlIntgErrNone]	full_word	auto[0]	3682422	1			T1	13598		T3	2135		T6	270
auto[TlIntgErrNone]	full_word	auto[1]	5184349	1			T1	27826		T2	6		T3	197
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T272	2		T273	3		T274	2
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T272	4		T273	5		T274	6
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T363	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T281	1		T367	1		T366	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T272	5		T273	5		T274	3
auto[TlIntgErrData]	partial	auto[1]	59	1			T272	1		T273	4		T274	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T272	2		T274	1		T362	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T368	1		T369	1		T367	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T272	4		T274	3		T282	2
auto[TlIntgErrBoth]	partial	auto[1]	36	1			T272	2		T273	2		T274	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T274	1		T368	1		T370	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T273	1		T371	1		T365	1