Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.17	94.16	96.15	96.94		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	499791679	9013268	0	0
check_regwen_rd_A	499791679	3408	0	0
check_timeout_rd_A	499791679	2754	0	0
check_trigger_regwen_rd_A	499791679	3314	0	0
consistency_check_period_rd_A	499791679	3625	0	0
creator_sw_cfg_read_lock_rd_A	499791679	3019	0	0
direct_access_address_rd_A	499791679	1933	0	0
direct_access_wdata_0_rd_A	499791679	1165	0	0
direct_access_wdata_1_rd_A	499791679	1254	0	0
integrity_check_period_rd_A	499791679	3468	0	0
intr_enable_rd_A	499791679	4064	0	0
owner_sw_cfg_read_lock_rd_A	499791679	2829	0	0
rot_creator_auth_codesign_read_lock_rd_A	499791679	2712	0	0
rot_creator_auth_state_read_lock_rd_A	499791679	2851	0	0
vendor_test_read_lock_rd_A	499791679	2808	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499791679	9013268	0	0
T1	666130	48267	0	0
T2	5515	0	0	0
T3	44290	0	0	0
T4	49673	0	0	0
T5	13926	0	0	0
T6	9289	0	0	0
T7	12222	0	0	0
T8	576854	105871	0	0
T9	0	49796	0	0
T10	0	192345	0	0
T11	0	55239	0	0
T12	0	164885	0	0
T16	11280	0	0	0
T17	264736	0	0	0
T110	0	220940	0	0
T138	0	130009	0	0
T148	0	44316	0	0
T242	0	180236	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499791679	3408	0	0
T1	666130	39	0	0
T2	5515	0	0	0
T3	44290	0	0	0
T4	49673	0	0	0
T5	13926	0	0	0
T6	9289	0	0	0
T7	12222	0	0	0
T8	576854	163	0	0
T16	11280	0	0	0
T17	264736	0	0	0
T222	0	45	0	0
T257	0	23	0	0
T258	0	100	0	0
T301	0	101	0	0
T352	0	25	0	0
T353	0	147	0	0
T354	0	20	0	0
T355	0	143	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499791679	2754	0	0
T1	666130	27	0	0
T2	5515	0	0	0
T3	44290	0	0	0
T4	49673	0	0	0
T5	13926	0	0	0
T6	9289	0	0	0
T7	12222	0	0	0
T8	576854	127	0	0
T16	11280	0	0	0
T17	264736	0	0	0
T222	0	121	0	0
T257	0	34	0	0
T258	0	65	0	0
T301	0	139	0	0
T352	0	36	0	0
T353	0	140	0	0
T354	0	43	0	0
T355	0	187	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499791679	3314	0	0
T1	666130	31	0	0
T2	5515	0	0	0
T3	44290	0	0	0
T4	49673	0	0	0
T5	13926	0	0	0
T6	9289	0	0	0
T7	12222	0	0	0
T8	576854	126	0	0
T16	11280	0	0	0
T17	264736	0	0	0
T222	0	59	0	0
T257	0	15	0	0
T258	0	75	0	0
T301	0	136	0	0
T352	0	24	0	0
T353	0	152	0	0
T354	0	53	0	0
T355	0	192	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499791679	3625	0	0
T1	666130	34	0	0
T2	5515	0	0	0
T3	44290	0	0	0
T4	49673	0	0	0
T5	13926	0	0	0
T6	9289	0	0	0
T7	12222	0	0	0
T8	576854	149	0	0
T16	11280	0	0	0
T17	264736	0	0	0
T222	0	56	0	0
T257	0	12	0	0
T258	0	96	0	0
T301	0	84	0	0
T352	0	21	0	0
T353	0	137	0	0
T354	0	35	0	0
T355	0	184	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499791679	3019	0	0
T1	666130	35	0	0
T2	5515	0	0	0
T3	44290	0	0	0
T4	49673	0	0	0
T5	13926	0	0	0
T6	9289	0	0	0
T7	12222	0	0	0
T8	576854	91	0	0
T16	11280	0	0	0
T17	264736	0	0	0
T222	0	72	0	0
T257	0	17	0	0
T258	0	94	0	0
T301	0	149	0	0
T352	0	26	0	0
T353	0	145	0	0
T354	0	36	0	0
T355	0	212	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499791679	1933	0	0
T1	666130	56	0	0
T2	5515	0	0	0
T3	44290	0	0	0
T4	49673	0	0	0
T5	13926	0	0	0
T6	9289	0	0	0
T7	12222	0	0	0
T8	576854	160	0	0
T16	11280	0	0	0
T17	264736	0	0	0
T222	0	60	0	0
T257	0	21	0	0
T258	0	101	0	0
T301	0	145	0	0
T352	0	21	0	0
T353	0	184	0	0
T354	0	42	0	0
T355	0	187	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499791679	1165	0	0
T1	666130	25	0	0
T2	5515	0	0	0
T3	44290	0	0	0
T4	49673	0	0	0
T5	13926	0	0	0
T6	9289	0	0	0
T7	12222	0	0	0
T8	576854	104	0	0
T16	11280	0	0	0
T17	264736	0	0	0
T222	0	51	0	0
T257	0	18	0	0
T258	0	46	0	0
T301	0	134	0	0
T352	0	18	0	0
T353	0	65	0	0
T354	0	20	0	0
T355	0	170	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499791679	1254	0	0
T1	666130	38	0	0
T2	5515	0	0	0
T3	44290	0	0	0
T4	49673	0	0	0
T5	13926	0	0	0
T6	9289	0	0	0
T7	12222	0	0	0
T8	576854	84	0	0
T16	11280	0	0	0
T17	264736	0	0	0
T222	0	45	0	0
T257	0	8	0	0
T258	0	94	0	0
T301	0	101	0	0
T352	0	41	0	0
T353	0	94	0	0
T354	0	2	0	0
T355	0	94	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499791679	3468	0	0
T1	666130	52	0	0
T2	5515	0	0	0
T3	44290	0	0	0
T4	49673	0	0	0
T5	13926	0	0	0
T6	9289	0	0	0
T7	12222	0	0	0
T8	576854	124	0	0
T16	11280	0	0	0
T17	264736	0	0	0
T222	0	56	0	0
T257	0	37	0	0
T258	0	61	0	0
T301	0	102	0	0
T352	0	38	0	0
T353	0	132	0	0
T354	0	32	0	0
T355	0	189	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499791679	4064	0	0
T1	666130	50	0	0
T2	5515	0	0	0
T3	44290	0	0	0
T4	49673	0	0	0
T5	13926	0	0	0
T6	9289	0	0	0
T7	12222	0	0	0
T8	576854	171	0	0
T16	11280	0	0	0
T17	264736	0	0	0
T222	0	108	0	0
T257	0	21	0	0
T258	0	43	0	0
T301	0	128	0	0
T352	0	48	0	0
T353	0	161	0	0
T354	0	34	0	0
T356	0	45	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499791679	2829	0	0
T1	666130	36	0	0
T2	5515	0	0	0
T3	44290	0	0	0
T4	49673	0	0	0
T5	13926	0	0	0
T6	9289	0	0	0
T7	12222	0	0	0
T8	576854	120	0	0
T16	11280	0	0	0
T17	264736	0	0	0
T222	0	58	0	0
T257	0	22	0	0
T258	0	67	0	0
T301	0	140	0	0
T352	0	35	0	0
T353	0	179	0	0
T354	0	12	0	0
T355	0	156	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499791679	2712	0	0
T1	666130	78	0	0
T2	5515	0	0	0
T3	44290	0	0	0
T4	49673	0	0	0
T5	13926	0	0	0
T6	9289	0	0	0
T7	12222	0	0	0
T8	576854	121	0	0
T16	11280	0	0	0
T17	264736	0	0	0
T222	0	61	0	0
T257	0	14	0	0
T258	0	74	0	0
T301	0	93	0	0
T352	0	46	0	0
T353	0	140	0	0
T354	0	26	0	0
T355	0	186	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499791679	2851	0	0
T1	666130	19	0	0
T2	5515	0	0	0
T3	44290	0	0	0
T4	49673	0	0	0
T5	13926	0	0	0
T6	9289	0	0	0
T7	12222	0	0	0
T8	576854	158	0	0
T16	11280	0	0	0
T17	264736	0	0	0
T222	0	53	0	0
T257	0	43	0	0
T258	0	73	0	0
T301	0	128	0	0
T352	0	33	0	0
T353	0	152	0	0
T354	0	40	0	0
T355	0	171	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499791679	2808	0	0
T1	666130	25	0	0
T2	5515	0	0	0
T3	44290	0	0	0
T4	49673	0	0	0
T5	13926	0	0	0
T6	9289	0	0	0
T7	12222	0	0	0
T8	576854	116	0	0
T16	11280	0	0	0
T17	264736	0	0	0
T222	0	70	0	0
T257	0	26	0	0
T258	0	80	0	0
T301	0	111	0	0
T352	0	45	0	0
T353	0	179	0	0
T354	0	11	0	0
T355	0	164	0	0