Assertions
dashboard | hierarchy | modlist | groups | tests | asserts
Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total1457020
Category 01457020

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total1457020
Severity 01457020

Summary for Assertions
NUMBERPERCENT
Total Number1457100.00
Uncovered543.71
Success140396.29
Failure00.00
Incomplete110.75
Without Attempts50.34

Summary for Cover Sequences
NUMBERPERCENT
Total Number20100.00
Uncovered00.00
All Matches20100.00
First Matches20100.00
Go previous page
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETE
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.EccKnown_A 0043609256243522165100
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.RDataOutKnown_A 0043609256243522165100
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A 001145114500
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A 0043609256243522165100
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A 0043609256243522165100
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_state_regs.AssertConnected_A 001145114500
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_state_regs_A 0043609256243522165100
tb.dut.gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A 004360925625000
tb.dut.gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A 004360925625000
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.AccessKnown_A 0043609256243522165100
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.BypassEnable1_A 0043609256243522165100
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.CnstyChkAckKnown_A 0043609256243522165100
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.DataKnown_A 0043609256243522165100
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.DigestKnown_A 0043609256243522165100
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.DigestOffsetMustBeRepresentable_A 001145114500
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ErrorKnown_A 0043609256243522165100
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.InitDoneKnown_A 0043609256243522165100
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.InitReadLocksPartition_A 004360925628415068600
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.InitWriteLocksPartition_A 004360925628415068600
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.IntegChkAckKnown_A 0043609256243522165100
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OffsetMustBeBlockAligned_A 001145114500
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpAddrKnown_A 0043609256243522165100
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpCmdKnown_A 0043609256243522165100
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpPartBufSize_A 001145114500
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpReqKnown_A 0043609256243522165100
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpSizeKnown_A 0043609256243522165100
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpWdataKnown_A 0043609256243522165100
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ReadLockImpliesDigest_A 0043609256243522165100
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ScrmblCmdKnown_A 0043609256243522165100
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ScrmblDataKnown_A 0043413662243330914800
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ScrmblModeKnown_A 0043609256243522165100
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ScrmblMtxReqKnown_A 0043609256243522165100
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ScrmblSelKnown_A 0043609256243522165100
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ScrmblValidKnown_A 0043609256243522165100
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.SizeMustBeBlockAligned_A 001145114500
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.WriteLockPropagation_A 00436092562225377000
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_write_lock.DigestWriteLocksPartition_A 004360925622534438400
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A 0043609256243522165100
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataKnown_A 0043609256243522165100
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataOutKnown_A 0043609256243522165100
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccErrKnown_A 0043609256243522165100
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccKnown_A 0043609256243522165100
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.RDataOutKnown_A 0043609256243522165100
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A 001145114500
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A 0043609256243522165100
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A 0043609256243522165100
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_state_regs.AssertConnected_A 001145114500
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_state_regs_A 0043609256243522165100
tb.dut.gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A 004360925625000
tb.dut.gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A 004360925625000
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.AccessKnown_A 0043609256243522165100
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.BypassEnable1_A 0043609256243522165100
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.CnstyChkAckKnown_A 0043609256243522165100
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.DataKnown_A 0043609256243522165100
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.DigestKnown_A 0043609256243522165100
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.DigestOffsetMustBeRepresentable_A 001145114500
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ErrorKnown_A 0043609256243522165100
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.InitDoneKnown_A 0043609256243522165100
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.InitReadLocksPartition_A 004360925627657549500
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.InitWriteLocksPartition_A 004360925627657549500
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.IntegChkAckKnown_A 0043609256243522165100
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OffsetMustBeBlockAligned_A 001145114500
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpAddrKnown_A 0043609256243522165100
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpCmdKnown_A 0043609256243522165100
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpPartBufSize_A 001145114500
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpReqKnown_A 0043609256243522165100
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpSizeKnown_A 0043609256243522165100
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpWdataKnown_A 0043609256243522165100
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ReadLockImpliesDigest_A 0043609256243522165100
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ScrmblCmdKnown_A 0043609256243522165100
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ScrmblDataKnown_A 0043413662243330914800
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ScrmblModeKnown_A 0043609256243522165100
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ScrmblMtxReqKnown_A 0043609256243522165100
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ScrmblSelKnown_A 0043609256243522165100
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ScrmblValidKnown_A 0043609256243522165100
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.SizeMustBeBlockAligned_A 001145114500
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.WriteLockPropagation_A 00436092562243886900
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_write_lock.DigestWriteLocksPartition_A 004360925622731135800
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A 0043609256243522165100
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataKnown_A 0043609256243522165100
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataOutKnown_A 0043609256243522165100
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccErrKnown_A 0043609256243522165100
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccKnown_A 0043609256243522165100
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.RDataOutKnown_A 0043609256243522165100
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A 001145114500
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A 0043609256243522165100
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A 0043609256243522165100
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_state_regs.AssertConnected_A 001145114500
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_state_regs_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.FpvSecCmCntPartBufCheck_A 004360925625000
tb.dut.gen_partitions[7].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A 004360925625000
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.AccessKnown_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.BypassEnable0_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.BypassEnable1_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.CnstyChkAckKnown_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.DataKnown_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.DigestKnown_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.DigestOffsetMustBeRepresentable_A 001145114500
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ErrorKnown_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.InitDoneKnown_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.InitReadLocksPartition_A 004360925628194548200
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.InitWriteLocksPartition_A 004360925628194548200
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.IntegChkAckKnown_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OffsetMustBeBlockAligned_A 001145114500
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OtpAddrKnown_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OtpCmdKnown_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OtpPartBufSize_A 001145114500
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OtpReqKnown_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OtpSizeKnown_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OtpWdataKnown_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ReadLockImpliesDigest_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ReadLockPropagation_A 00436092562244792600
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ScrambledImpliesDigest_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ScrmblCmdKnown_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ScrmblDataKnown_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ScrmblModeKnown_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ScrmblMtxReqKnown_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ScrmblSelKnown_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ScrmblValidKnown_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.SizeMustBeBlockAligned_A 001145114500
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.WriteLockImpliesDigest_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.WriteLockPropagation_A 00436092562270460400
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_read_lock.DigestReadLocksPartition_A 004360925622578444900
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock.OutputsKnown_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_write_lock.DigestWriteLocksPartition_A 004360925622578444900
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataKnown_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataOutKnown_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccErrKnown_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccKnown_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.RDataOutKnown_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A 001145114500
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A 0043609256243522165100
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_state_regs.AssertConnected_A 001145114500
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_state_regs_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.FpvSecCmCntPartBufCheck_A 004360925625000
tb.dut.gen_partitions[8].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A 004360925625000
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.AccessKnown_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.BypassEnable0_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.BypassEnable1_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.CnstyChkAckKnown_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.DataKnown_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.DigestKnown_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.DigestOffsetMustBeRepresentable_A 001145114500
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ErrorKnown_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.InitDoneKnown_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.InitReadLocksPartition_A 004360925629178017200
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.InitWriteLocksPartition_A 004360925629178017200
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.IntegChkAckKnown_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OffsetMustBeBlockAligned_A 001145114500
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OtpAddrKnown_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OtpCmdKnown_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OtpPartBufSize_A 001145114500
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OtpReqKnown_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OtpSizeKnown_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OtpWdataKnown_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ReadLockImpliesDigest_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ReadLockPropagation_A 00436092562245856400
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ScrambledImpliesDigest_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ScrmblCmdKnown_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ScrmblDataKnown_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ScrmblModeKnown_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ScrmblMtxReqKnown_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ScrmblSelKnown_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ScrmblValidKnown_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.SizeMustBeBlockAligned_A 001145114500
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.WriteLockImpliesDigest_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.WriteLockPropagation_A 00436092562222450000
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_read_lock.DigestReadLocksPartition_A 004360925622283126800
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock.OutputsKnown_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_write_lock.DigestWriteLocksPartition_A 004360925622283126800
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataKnown_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataOutKnown_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccErrKnown_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccKnown_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.RDataOutKnown_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A 001145114500
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A 0043609256243522165100
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_state_regs.AssertConnected_A 001145114500
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_state_regs_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.FpvSecCmCntPartBufCheck_A 004360925625000
tb.dut.gen_partitions[9].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A 004360925625000
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.AccessKnown_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.BypassEnable0_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.BypassEnable1_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.CnstyChkAckKnown_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.DataKnown_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.DigestKnown_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.DigestOffsetMustBeRepresentable_A 001145114500
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ErrorKnown_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.InitDoneKnown_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.InitReadLocksPartition_A 004360925629613404900
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.InitWriteLocksPartition_A 004360925629613404900
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.IntegChkAckKnown_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OffsetMustBeBlockAligned_A 001145114500
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OtpAddrKnown_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OtpCmdKnown_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OtpPartBufSize_A 001145114500
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OtpReqKnown_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OtpSizeKnown_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OtpWdataKnown_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ReadLockImpliesDigest_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ReadLockPropagation_A 0043609256222329202200
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ScrambledImpliesDigest_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ScrmblCmdKnown_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ScrmblDataKnown_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ScrmblModeKnown_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ScrmblMtxReqKnown_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ScrmblSelKnown_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ScrmblValidKnown_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.SizeMustBeBlockAligned_A 001145114500
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.WriteLockImpliesDigest_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.WriteLockPropagation_A 0043609256222313081100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_read_lock.DigestReadLocksPartition_A 004360925621608857400
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock.OutputsKnown_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_write_lock.DigestWriteLocksPartition_A 004360925621608857400
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataKnown_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataOutKnown_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccErrKnown_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccKnown_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.RDataOutKnown_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A 001145114500
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A 0043609256243522165100
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_state_regs.AssertConnected_A 001145114500
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_state_regs_A 0043609256243522165100
tb.dut.gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A 004360925625000
tb.dut.gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A 004360925625000
tb.dut.otp_ctrl_core_csr_assert.TlulOOBAddrErr_A 00439258479743096200
tb.dut.otp_ctrl_core_csr_assert.check_regwen_rd_A 00439258479225500
tb.dut.otp_ctrl_core_csr_assert.check_timeout_rd_A 00439258479142100
tb.dut.otp_ctrl_core_csr_assert.check_trigger_regwen_rd_A 00439258479241000
tb.dut.otp_ctrl_core_csr_assert.consistency_check_period_rd_A 00439258479254100
tb.dut.otp_ctrl_core_csr_assert.creator_sw_cfg_read_lock_rd_A 00439258479130900
tb.dut.otp_ctrl_core_csr_assert.direct_access_address_rd_A 00439258479135200
tb.dut.otp_ctrl_core_csr_assert.direct_access_wdata_0_rd_A 0043925847977000
tb.dut.otp_ctrl_core_csr_assert.direct_access_wdata_1_rd_A 0043925847984100
tb.dut.otp_ctrl_core_csr_assert.integrity_check_period_rd_A 00439258479232000
tb.dut.otp_ctrl_core_csr_assert.intr_enable_rd_A 00439258479307300
tb.dut.otp_ctrl_core_csr_assert.owner_sw_cfg_read_lock_rd_A 00439258479126100
tb.dut.otp_ctrl_core_csr_assert.rot_creator_auth_codesign_read_lock_rd_A 00439258479134300
tb.dut.otp_ctrl_core_csr_assert.rot_creator_auth_state_read_lock_rd_A 00439258479113700
tb.dut.otp_ctrl_core_csr_assert.vendor_test_read_lock_rd_A 00439258479129700
tb.dut.prim_tlul_assert_device.aKnown_A 004392584793189866000
tb.dut.prim_tlul_assert_device.aKnown_AKnownEnable 0043925847943833420300
tb.dut.prim_tlul_assert_device.aReadyKnown_A 0043925847943833420300
tb.dut.prim_tlul_assert_device.dKnown_A 004392584793272336000
tb.dut.prim_tlul_assert_device.dKnown_AKnownEnable 0043925847943833420300
tb.dut.prim_tlul_assert_device.dReadyKnown_A 0043925847943833420300
tb.dut.prim_tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A 001319131900
tb.dut.prim_tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A 001319131900
Go next page
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%