Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.18	94.16	96.15	97.00		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.18	94.16	96.15	97.00		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T160,T123

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T128,T158

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T17,T18,T19

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T60,T149,T161
1	Covered	T60,T149,T161

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T8

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T8

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T4
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T4
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T113,T102,T179
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T105,T112,T176
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T2,T4
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T155,T209,T210
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T59,T60,T61
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T2,T4
CheckFailError	317	Covered	T60,T149,T161
FsmStateError	289	Covered	T1,T2,T4
MacroEccCorrError	221	Covered	T7,T8,T128
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T1,T4,T13
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T2,T4
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T60,T149,T161
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T4
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T7,T128,T158
MacroEccCorrError->NoError	235	Covered	T8,T36,T58
NoError->AccessError	256	Covered	T1,T2,T4
NoError->CheckFailError	317	Covered	T60,T149,T161
NoError->FsmStateError	289	Covered	T1,T2,T6
NoError->MacroEccCorrError	221	Covered	T7,T8,T128

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T7,T160,T123
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T176,T183,T188
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T4,T90,T56
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T8,T128,T158
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T155,T209,T210
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T17,T18,T19
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T2,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T60,T149,T161
1	0	Covered	T60,T149,T161
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	436092562	435221651	0	0
DigestKnown_A	436092562	435221651	0	0
DigestOffsetMustBeRepresentable_A	1145	1145	0	0
EccErrorState_A	436092562	10102	0	0
ErrorKnown_A	436092562	435221651	0	0
FsmStateKnown_A	436092562	435221651	0	0
InitDoneKnown_A	436092562	435221651	0	0
InitReadLocksPartition_A	436092562	74127645	0	0
InitWriteLocksPartition_A	436092562	74127645	0	0
OffsetMustBeBlockAligned_A	1145	1145	0	0
OtpAddrKnown_A	436092562	435221651	0	0
OtpCmdKnown_A	436092562	435221651	0	0
OtpErrorState_A	436092562	51	0	0
OtpReqKnown_A	436092562	435221651	0	0
OtpSizeKnown_A	436092562	435221651	0	0
OtpWdataKnown_A	436092562	435221651	0	0
ReadLockPropagation_A	436092562	176649699	0	0
SizeMustBeBlockAligned_A	1145	1145	0	0
TlulGntKnown_A	436092562	435221651	0	0
TlulRdataKnown_A	436092562	435221651	0	0
TlulReadOnReadLock_A	436092562	7951	0	0
TlulRerrorKnown_A	436092562	435221651	0	0
TlulRvalidKnown_A	436092562	435221651	0	0
WriteLockPropagation_A	436092562	2212870	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	436092562	27126840	0	0
u_state_regs_A	436092562	435221651	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	435221651	0	0
T1	556043	553988	0	0
T2	591032	591017	0	0
T3	10119	9848	0	0
T4	208103	208092	0	0
T5	40605	39583	0	0
T6	58847	57874	0	0
T7	9847	9572	0	0
T8	48110	47394	0	0
T9	13328	13164	0	0
T10	20096	19912	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	435221651	0	0
T1	556043	553988	0	0
T2	591032	591017	0	0
T3	10119	9848	0	0
T4	208103	208092	0	0
T5	40605	39583	0	0
T6	58847	57874	0	0
T7	9847	9572	0	0
T8	48110	47394	0	0
T9	13328	13164	0	0
T10	20096	19912	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1145	1145	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	10102	0	0
T22	11234	0	0	0
T41	50848	0	0	0
T60	12069	3270	0	0
T61	998385	0	0	0
T149	0	3883	0	0
T161	0	2949	0	0
T170	482748	0	0	0
T171	36361	0	0	0
T172	5094	0	0	0
T173	22134	0	0	0
T174	12079	0	0	0
T175	289083	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	435221651	0	0
T1	556043	553988	0	0
T2	591032	591017	0	0
T3	10119	9848	0	0
T4	208103	208092	0	0
T5	40605	39583	0	0
T6	58847	57874	0	0
T7	9847	9572	0	0
T8	48110	47394	0	0
T9	13328	13164	0	0
T10	20096	19912	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	435221651	0	0
T1	556043	553988	0	0
T2	591032	591017	0	0
T3	10119	9848	0	0
T4	208103	208092	0	0
T5	40605	39583	0	0
T6	58847	57874	0	0
T7	9847	9572	0	0
T8	48110	47394	0	0
T9	13328	13164	0	0
T10	20096	19912	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	435221651	0	0
T1	556043	553988	0	0
T2	591032	591017	0	0
T3	10119	9848	0	0
T4	208103	208092	0	0
T5	40605	39583	0	0
T6	58847	57874	0	0
T7	9847	9572	0	0
T8	48110	47394	0	0
T9	13328	13164	0	0
T10	20096	19912	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	74127645	0	0
T1	556043	86679	0	0
T2	591032	37526	0	0
T3	10119	296	0	0
T4	208103	726583	0	0
T5	40605	1624	0	0
T6	58847	13825	0	0
T7	9847	3445	0	0
T8	48110	4516	0	0
T9	13328	4630	0	0
T10	20096	326	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	74127645	0	0
T1	556043	86679	0	0
T2	591032	37526	0	0
T3	10119	296	0	0
T4	208103	726583	0	0
T5	40605	1624	0	0
T6	58847	13825	0	0
T7	9847	3445	0	0
T8	48110	4516	0	0
T9	13328	4630	0	0
T10	20096	326	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1145	1145	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	435221651	0	0
T1	556043	553988	0	0
T2	591032	591017	0	0
T3	10119	9848	0	0
T4	208103	208092	0	0
T5	40605	39583	0	0
T6	58847	57874	0	0
T7	9847	9572	0	0
T8	48110	47394	0	0
T9	13328	13164	0	0
T10	20096	19912	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	435221651	0	0
T1	556043	553988	0	0
T2	591032	591017	0	0
T3	10119	9848	0	0
T4	208103	208092	0	0
T5	40605	39583	0	0
T6	58847	57874	0	0
T7	9847	9572	0	0
T8	48110	47394	0	0
T9	13328	13164	0	0
T10	20096	19912	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	51	0	0
T34	13138	0	0	0
T65	15255	0	0	0
T101	11933	0	0	0
T154	65228	0	0	0
T155	0	1	0	0
T159	35323	0	0	0
T176	8793	1	0	0
T177	10560	0	0	0
T183	0	1	0	0
T188	0	1	0	0
T190	81486	0	0	0
T191	6412	0	0	0
T192	4851	0	0	0
T211	0	1	0	0
T212	0	1	0	0
T213	0	1	0	0
T214	0	1	0	0
T215	0	1	0	0
T216	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	435221651	0	0
T1	556043	553988	0	0
T2	591032	591017	0	0
T3	10119	9848	0	0
T4	208103	208092	0	0
T5	40605	39583	0	0
T6	58847	57874	0	0
T7	9847	9572	0	0
T8	48110	47394	0	0
T9	13328	13164	0	0
T10	20096	19912	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	435221651	0	0
T1	556043	553988	0	0
T2	591032	591017	0	0
T3	10119	9848	0	0
T4	208103	208092	0	0
T5	40605	39583	0	0
T6	58847	57874	0	0
T7	9847	9572	0	0
T8	48110	47394	0	0
T9	13328	13164	0	0
T10	20096	19912	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	435221651	0	0
T1	556043	553988	0	0
T2	591032	591017	0	0
T3	10119	9848	0	0
T4	208103	208092	0	0
T5	40605	39583	0	0
T6	58847	57874	0	0
T7	9847	9572	0	0
T8	48110	47394	0	0
T9	13328	13164	0	0
T10	20096	19912	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	176649699	0	0
T1	556043	92622	0	0
T2	591032	138019	0	0
T3	10119	0	0	0
T4	208103	921826	0	0
T5	40605	3761	0	0
T6	58847	3227	0	0
T7	9847	0	0	0
T8	48110	9696	0	0
T9	13328	0	0	0
T10	20096	10377	0	0
T14	0	14025	0	0
T95	0	4485	0	0
T100	0	3432	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1145	1145	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	435221651	0	0
T1	556043	553988	0	0
T2	591032	591017	0	0
T3	10119	9848	0	0
T4	208103	208092	0	0
T5	40605	39583	0	0
T6	58847	57874	0	0
T7	9847	9572	0	0
T8	48110	47394	0	0
T9	13328	13164	0	0
T10	20096	19912	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	435221651	0	0
T1	556043	553988	0	0
T2	591032	591017	0	0
T3	10119	9848	0	0
T4	208103	208092	0	0
T5	40605	39583	0	0
T6	58847	57874	0	0
T7	9847	9572	0	0
T8	48110	47394	0	0
T9	13328	13164	0	0
T10	20096	19912	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	7951	0	0
T1	556043	19	0	0
T2	591032	53	0	0
T3	10119	0	0	0
T4	208103	14	0	0
T5	40605	1	0	0
T6	58847	3	0	0
T7	9847	0	0	0
T8	48110	8	0	0
T9	13328	0	0	0
T10	20096	1	0	0
T14	0	39	0	0
T95	0	1	0	0
T99	0	13	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	435221651	0	0
T1	556043	553988	0	0
T2	591032	591017	0	0
T3	10119	9848	0	0
T4	208103	208092	0	0
T5	40605	39583	0	0
T6	58847	57874	0	0
T7	9847	9572	0	0
T8	48110	47394	0	0
T9	13328	13164	0	0
T10	20096	19912	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	435221651	0	0
T1	556043	553988	0	0
T2	591032	591017	0	0
T3	10119	9848	0	0
T4	208103	208092	0	0
T5	40605	39583	0	0
T6	58847	57874	0	0
T7	9847	9572	0	0
T8	48110	47394	0	0
T9	13328	13164	0	0
T10	20096	19912	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	2212870	0	0
T1	556043	15111	0	0
T2	591032	0	0	0
T3	10119	0	0	0
T4	208103	0	0	0
T5	40605	1438	0	0
T6	58847	0	0	0
T7	9847	0	0	0
T8	48110	0	0	0
T9	13328	0	0	0
T10	20096	0	0	0
T12	0	7379	0	0
T14	0	5618	0	0
T36	0	8150	0	0
T56	0	18049	0	0
T89	0	21707	0	0
T90	0	24261	0	0
T92	0	6207	0	0
T93	0	64524	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	27126840	0	0
T1	556043	294226	0	0
T2	591032	0	0	0
T3	10119	0	0	0
T4	208103	0	0	0
T5	40605	32683	0	0
T6	58847	0	0	0
T7	9847	0	0	0
T8	48110	34324	0	0
T9	13328	0	0	0
T10	20096	5223	0	0
T12	0	161246	0	0
T14	0	132936	0	0
T97	0	22648	0	0
T100	0	18726	0	0
T158	0	4640	0	0
T200	0	2665	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	435221651	0	0
T1	556043	553988	0	0
T2	591032	591017	0	0
T3	10119	9848	0	0
T4	208103	208092	0	0
T5	40605	39583	0	0
T6	58847	57874	0	0
T7	9847	9572	0	0
T8	48110	47394	0	0
T9	13328	13164	0	0
T10	20096	19912	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T34,T66,T67

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T128,T165,T63

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T17,T18,T19

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T60,T149,T162
1	Covered	T60,T149,T162

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T4

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T90,T55

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T90,T55

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T4
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T4
ReadWaitSt	252	Covered	T1,T2,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T4
IdleSt->ReadSt	236	Covered	T1,T2,T4
InitSt->ErrorSt	315	Covered	T105,T112,T113
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T176,T163,T202
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T2,T4
ReadSt->ReadWaitSt	252	Covered	T1,T2,T4
ReadWaitSt->ErrorSt	276	Covered	T154,T185,T217
ReadWaitSt->IdleSt	270	Covered	T1,T2,T4
ResetSt->ErrorSt	315	Covered	T59,T60,T61
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T2,T4
CheckFailError	317	Covered	T60,T149,T162
FsmStateError	289	Covered	T1,T2,T4
MacroEccCorrError	221	Covered	T128,T34,T66
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T4,T13,T158
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T2,T4
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T60,T149,T162
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T4
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T128,T34,T66
MacroEccCorrError->NoError	235	Covered	T63,T36,T166
NoError->AccessError	256	Covered	T1,T2,T4
NoError->CheckFailError	317	Covered	T60,T149,T162
NoError->FsmStateError	289	Covered	T1,T2,T6
NoError->MacroEccCorrError	221	Covered	T128,T34,T66

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T90,T55
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T34,T66,T67
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T163,T202,T218
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T14,T12,T90
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T128,T165,T63
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T154,T185,T217
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T17,T18,T19
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T2,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T60,T149,T162
1	0	Covered	T60,T149,T162
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	436092562	435221651	0	0
DigestKnown_A	436092562	435221651	0	0
DigestOffsetMustBeRepresentable_A	1145	1145	0	0
EccErrorState_A	436092562	16607	0	0
ErrorKnown_A	436092562	435221651	0	0
FsmStateKnown_A	436092562	435221651	0	0
InitDoneKnown_A	436092562	435221651	0	0
InitReadLocksPartition_A	436092562	74308129	0	0
InitWriteLocksPartition_A	436092562	74308129	0	0
OffsetMustBeBlockAligned_A	1145	1145	0	0
OtpAddrKnown_A	436092562	435221651	0	0
OtpCmdKnown_A	436092562	435221651	0	0
OtpErrorState_A	436092562	38	0	0
OtpReqKnown_A	436092562	435221651	0	0
OtpSizeKnown_A	436092562	435221651	0	0
OtpWdataKnown_A	436092562	435221651	0	0
ReadLockPropagation_A	436092562	180905726	0	0
SizeMustBeBlockAligned_A	1145	1145	0	0
TlulGntKnown_A	436092562	435221651	0	0
TlulRdataKnown_A	436092562	435221651	0	0
TlulReadOnReadLock_A	436092562	7492	0	0
TlulRerrorKnown_A	436092562	435221651	0	0
TlulRvalidKnown_A	436092562	435221651	0	0
WriteLockPropagation_A	436092562	1012939	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	436092562	13143341	0	0
u_state_regs_A	436092562	435221651	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	435221651	0	0
T1	556043	553988	0	0
T2	591032	591017	0	0
T3	10119	9848	0	0
T4	208103	208092	0	0
T5	40605	39583	0	0
T6	58847	57874	0	0
T7	9847	9572	0	0
T8	48110	47394	0	0
T9	13328	13164	0	0
T10	20096	19912	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	435221651	0	0
T1	556043	553988	0	0
T2	591032	591017	0	0
T3	10119	9848	0	0
T4	208103	208092	0	0
T5	40605	39583	0	0
T6	58847	57874	0	0
T7	9847	9572	0	0
T8	48110	47394	0	0
T9	13328	13164	0	0
T10	20096	19912	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1145	1145	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	16607	0	0
T22	11234	0	0	0
T41	50848	0	0	0
T60	12069	3270	0	0
T61	998385	0	0	0
T149	0	3883	0	0
T162	0	2949	0	0
T168	0	2778	0	0
T169	0	3727	0	0
T170	482748	0	0	0
T171	36361	0	0	0
T172	5094	0	0	0
T173	22134	0	0	0
T174	12079	0	0	0
T175	289083	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	435221651	0	0
T1	556043	553988	0	0
T2	591032	591017	0	0
T3	10119	9848	0	0
T4	208103	208092	0	0
T5	40605	39583	0	0
T6	58847	57874	0	0
T7	9847	9572	0	0
T8	48110	47394	0	0
T9	13328	13164	0	0
T10	20096	19912	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	435221651	0	0
T1	556043	553988	0	0
T2	591032	591017	0	0
T3	10119	9848	0	0
T4	208103	208092	0	0
T5	40605	39583	0	0
T6	58847	57874	0	0
T7	9847	9572	0	0
T8	48110	47394	0	0
T9	13328	13164	0	0
T10	20096	19912	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	435221651	0	0
T1	556043	553988	0	0
T2	591032	591017	0	0
T3	10119	9848	0	0
T4	208103	208092	0	0
T5	40605	39583	0	0
T6	58847	57874	0	0
T7	9847	9572	0	0
T8	48110	47394	0	0
T9	13328	13164	0	0
T10	20096	19912	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	74308129	0	0
T1	556043	87104	0	0
T2	591032	37713	0	0
T3	10119	330	0	0
T4	208103	726685	0	0
T5	40605	1845	0	0
T6	58847	14029	0	0
T7	9847	3496	0	0
T8	48110	4652	0	0
T9	13328	4664	0	0
T10	20096	377	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	74308129	0	0
T1	556043	87104	0	0
T2	591032	37713	0	0
T3	10119	330	0	0
T4	208103	726685	0	0
T5	40605	1845	0	0
T6	58847	14029	0	0
T7	9847	3496	0	0
T8	48110	4652	0	0
T9	13328	4664	0	0
T10	20096	377	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1145	1145	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	435221651	0	0
T1	556043	553988	0	0
T2	591032	591017	0	0
T3	10119	9848	0	0
T4	208103	208092	0	0
T5	40605	39583	0	0
T6	58847	57874	0	0
T7	9847	9572	0	0
T8	48110	47394	0	0
T9	13328	13164	0	0
T10	20096	19912	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	435221651	0	0
T1	556043	553988	0	0
T2	591032	591017	0	0
T3	10119	9848	0	0
T4	208103	208092	0	0
T5	40605	39583	0	0
T6	58847	57874	0	0
T7	9847	9572	0	0
T8	48110	47394	0	0
T9	13328	13164	0	0
T10	20096	19912	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	38	0	0
T101	11933	0	0	0
T102	18086	0	0	0
T103	19802	0	0	0
T141	34640	0	0	0
T154	65228	1	0	0
T156	0	1	0	0
T159	35323	0	0	0
T163	0	1	0	0
T185	0	1	0	0
T192	4851	0	0	0
T193	15328	0	0	0
T201	28219	0	0	0
T202	0	1	0	0
T217	0	1	0	0
T218	0	1	0	0
T219	0	1	0	0
T220	0	1	0	0
T221	0	1	0	0
T222	10293	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	435221651	0	0
T1	556043	553988	0	0
T2	591032	591017	0	0
T3	10119	9848	0	0
T4	208103	208092	0	0
T5	40605	39583	0	0
T6	58847	57874	0	0
T7	9847	9572	0	0
T8	48110	47394	0	0
T9	13328	13164	0	0
T10	20096	19912	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	435221651	0	0
T1	556043	553988	0	0
T2	591032	591017	0	0
T3	10119	9848	0	0
T4	208103	208092	0	0
T5	40605	39583	0	0
T6	58847	57874	0	0
T7	9847	9572	0	0
T8	48110	47394	0	0
T9	13328	13164	0	0
T10	20096	19912	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	435221651	0	0
T1	556043	553988	0	0
T2	591032	591017	0	0
T3	10119	9848	0	0
T4	208103	208092	0	0
T5	40605	39583	0	0
T6	58847	57874	0	0
T7	9847	9572	0	0
T8	48110	47394	0	0
T9	13328	13164	0	0
T10	20096	19912	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	180905726	0	0
T1	556043	91231	0	0
T2	591032	211647	0	0
T3	10119	0	0	0
T4	208103	939041	0	0
T5	40605	421	0	0
T6	58847	3225	0	0
T7	9847	0	0	0
T8	48110	8076	0	0
T9	13328	0	0	0
T10	20096	2473	0	0
T14	0	14099	0	0
T99	0	27698	0	0
T100	0	5400	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1145	1145	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	435221651	0	0
T1	556043	553988	0	0
T2	591032	591017	0	0
T3	10119	9848	0	0
T4	208103	208092	0	0
T5	40605	39583	0	0
T6	58847	57874	0	0
T7	9847	9572	0	0
T8	48110	47394	0	0
T9	13328	13164	0	0
T10	20096	19912	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	435221651	0	0
T1	556043	553988	0	0
T2	591032	591017	0	0
T3	10119	9848	0	0
T4	208103	208092	0	0
T5	40605	39583	0	0
T6	58847	57874	0	0
T7	9847	9572	0	0
T8	48110	47394	0	0
T9	13328	13164	0	0
T10	20096	19912	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	7492	0	0
T1	556043	19	0	0
T2	591032	48	0	0
T3	10119	0	0	0
T4	208103	11	0	0
T5	40605	0	0	0
T6	58847	4	0	0
T7	9847	0	0	0
T8	48110	3	0	0
T9	13328	0	0	0
T10	20096	0	0	0
T14	0	38	0	0
T95	0	1	0	0
T99	0	24	0	0
T100	0	1	0	0
T153	0	2	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	435221651	0	0
T1	556043	553988	0	0
T2	591032	591017	0	0
T3	10119	9848	0	0
T4	208103	208092	0	0
T5	40605	39583	0	0
T6	58847	57874	0	0
T7	9847	9572	0	0
T8	48110	47394	0	0
T9	13328	13164	0	0
T10	20096	19912	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	435221651	0	0
T1	556043	553988	0	0
T2	591032	591017	0	0
T3	10119	9848	0	0
T4	208103	208092	0	0
T5	40605	39583	0	0
T6	58847	57874	0	0
T7	9847	9572	0	0
T8	48110	47394	0	0
T9	13328	13164	0	0
T10	20096	19912	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	1012939	0	0
T12	380753	3141	0	0
T13	22604	0	0	0
T55	0	39460	0	0
T56	0	23738	0	0
T59	0	20918	0	0
T90	0	914	0	0
T92	0	5859	0	0
T97	35718	0	0	0
T105	15240	0	0	0
T112	11590	0	0	0
T113	12981	0	0	0
T128	53061	0	0	0
T158	89282	0	0	0
T195	0	19412	0	0
T196	0	28898	0	0
T197	0	2339	0	0
T198	0	33388	0	0
T199	4527	0	0	0
T203	4806	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	13143341	0	0
T12	380753	50683	0	0
T13	22604	0	0	0
T55	0	92409	0	0
T56	0	222929	0	0
T90	0	72926	0	0
T91	0	4605	0	0
T92	0	43303	0	0
T93	0	87673	0	0
T97	35718	0	0	0
T105	15240	0	0	0
T112	11590	0	0	0
T113	12981	0	0	0
T128	53061	0	0	0
T158	89282	0	0	0
T163	0	2212	0	0
T199	4527	0	0	0
T202	0	2812	0	0
T203	4806	0	0	0
T218	0	2923	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436092562	435221651	0	0
T1	556043	553988	0	0
T2	591032	591017	0	0
T3	10119	9848	0	0
T4	208103	208092	0	0
T5	40605	39583	0	0
T6	58847	57874	0	0
T7	9847	9572	0	0
T8	48110	47394	0	0
T9	13328	13164	0	0
T10	20096	19912	0	0