Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6940996	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6768593

1

T1

7389

T2

93137

T3

226

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8064067	1			T1	14994		T2	66660		T3	714
values[0x0]	2154298	1			T1	1320		T2	34809		T3	38
values[0x1]	3491224	1			T1	1246		T2	60954		T3	41

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4530513	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9179076

1

T1

9666

T2

123538

T3

378

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54374	1			T1	76		T2	584		T4	224
valid_sources[0x01]	53493	1			T1	68		T2	594		T4	220
valid_sources[0x02]	57021	1			T1	58		T2	608		T4	283
valid_sources[0x03]	48347	1			T1	61		T2	731		T4	219
valid_sources[0x04]	48518	1			T1	79		T2	661		T4	224
valid_sources[0x05]	53185	1			T1	63		T2	640		T4	217
valid_sources[0x06]	50450	1			T1	74		T2	560		T4	270
valid_sources[0x07]	52289	1			T1	60		T2	653		T4	251
valid_sources[0x08]	56704	1			T1	80		T2	674		T4	243
valid_sources[0x09]	47170	1			T1	72		T2	678		T4	237
valid_sources[0x0a]	48958	1			T1	57		T2	695		T4	258
valid_sources[0x0b]	48319	1			T1	90		T2	717		T4	250
valid_sources[0x0c]	84308	1			T1	89		T2	764		T4	257
valid_sources[0x0d]	50042	1			T1	59		T2	619		T4	227
valid_sources[0x0e]	54278	1			T1	69		T2	564		T4	265
valid_sources[0x0f]	45655	1			T1	60		T2	617		T4	227
valid_sources[0x10]	54254	1			T1	78		T2	720		T4	253
valid_sources[0x11]	55328	1			T1	76		T2	645		T4	247
valid_sources[0x12]	46855	1			T1	55		T2	652		T4	260
valid_sources[0x13]	50426	1			T1	70		T2	580		T4	196
valid_sources[0x14]	47152	1			T1	72		T2	647		T4	226
valid_sources[0x15]	45626	1			T1	57		T2	557		T4	278
valid_sources[0x16]	55786	1			T1	76		T2	623		T4	226
valid_sources[0x17]	94298	1			T1	67		T2	587		T4	234
valid_sources[0x18]	50147	1			T1	74		T2	816		T4	236
valid_sources[0x19]	58692	1			T1	75		T2	571		T4	237
valid_sources[0x1a]	48355	1			T1	73		T2	842		T4	257
valid_sources[0x1b]	47779	1			T1	76		T2	616		T4	267
valid_sources[0x1c]	47740	1			T1	72		T2	714		T4	233
valid_sources[0x1d]	47124	1			T1	71		T2	670		T4	227
valid_sources[0x1e]	61581	1			T1	73		T2	508		T4	245
valid_sources[0x1f]	54243	1			T1	58		T2	640		T4	277
valid_sources[0x20]	47378	1			T1	65		T2	526		T4	266
valid_sources[0x21]	52517	1			T1	76		T2	649		T4	248
valid_sources[0x22]	50318	1			T1	90		T2	574		T4	275
valid_sources[0x23]	44667	1			T1	65		T2	599		T4	278
valid_sources[0x24]	57908	1			T1	65		T2	454		T4	271
valid_sources[0x25]	46609	1			T1	63		T2	676		T4	234
valid_sources[0x26]	47013	1			T1	87		T2	565		T4	232
valid_sources[0x27]	52858	1			T1	67		T2	706		T4	262
valid_sources[0x28]	61241	1			T1	58		T2	738		T4	255
valid_sources[0x29]	49773	1			T1	80		T2	639		T4	274
valid_sources[0x2a]	47340	1			T1	70		T2	655		T4	225
valid_sources[0x2b]	54150	1			T1	69		T2	593		T4	252
valid_sources[0x2c]	47265	1			T1	69		T2	692		T4	234
valid_sources[0x2d]	48453	1			T1	64		T2	664		T4	232
valid_sources[0x2e]	58656	1			T1	66		T2	722		T4	250
valid_sources[0x2f]	48233	1			T1	66		T2	602		T4	240
valid_sources[0x30]	48752	1			T1	68		T2	636		T4	242
valid_sources[0x31]	47081	1			T1	68		T2	611		T4	219
valid_sources[0x32]	91709	1			T1	68		T2	607		T4	231
valid_sources[0x33]	62642	1			T1	67		T2	621		T4	236
valid_sources[0x34]	51714	1			T1	63		T2	835		T4	242
valid_sources[0x35]	46076	1			T1	51		T2	541		T4	249
valid_sources[0x36]	49048	1			T1	55		T2	635		T4	244
valid_sources[0x37]	117571	1			T1	69		T2	655		T4	254
valid_sources[0x38]	54093	1			T1	65		T2	549		T4	264
valid_sources[0x39]	51521	1			T1	73		T2	584		T4	236
valid_sources[0x3a]	46458	1			T1	74		T2	699		T4	257
valid_sources[0x3b]	49103	1			T1	82		T2	568		T4	253
valid_sources[0x3c]	53416	1			T1	63		T2	632		T4	220
valid_sources[0x3d]	48270	1			T1	63		T2	725		T4	222
valid_sources[0x3e]	103350	1			T1	65		T2	632		T4	241
valid_sources[0x3f]	49391	1			T1	64		T2	806		T4	247
valid_sources[0x40]	56050	1			T1	72		T2	571		T4	272
valid_sources[0x41]	60863	1			T1	65		T2	560		T4	236
valid_sources[0x42]	53249	1			T1	57		T2	601		T4	227
valid_sources[0x43]	64241	1			T1	59		T2	492		T4	210
valid_sources[0x44]	46571	1			T1	63		T2	624		T4	220
valid_sources[0x45]	46697	1			T1	63		T2	695		T4	198
valid_sources[0x46]	50467	1			T1	81		T2	527		T4	218
valid_sources[0x47]	48407	1			T1	64		T2	706		T4	224
valid_sources[0x48]	51104	1			T1	65		T2	625		T4	249
valid_sources[0x49]	52924	1			T1	77		T2	596		T4	266
valid_sources[0x4a]	49019	1			T1	76		T2	571		T4	251
valid_sources[0x4b]	46392	1			T1	74		T2	556		T4	238
valid_sources[0x4c]	52395	1			T1	71		T2	709		T4	271
valid_sources[0x4d]	49975	1			T1	67		T2	578		T4	226
valid_sources[0x4e]	53571	1			T1	68		T2	654		T3	793
valid_sources[0x4f]	57043	1			T1	67		T2	653		T4	278
valid_sources[0x50]	49826	1			T1	63		T2	731		T4	258
valid_sources[0x51]	59678	1			T1	56		T2	715		T4	209
valid_sources[0x52]	62669	1			T1	59		T2	570		T4	290
valid_sources[0x53]	48687	1			T1	76		T2	735		T4	242
valid_sources[0x54]	63490	1			T1	69		T2	562		T4	233
valid_sources[0x55]	58817	1			T1	87		T2	709		T4	228
valid_sources[0x56]	56049	1			T1	75		T2	725		T4	257
valid_sources[0x57]	51104	1			T1	54		T2	637		T4	209
valid_sources[0x58]	49945	1			T1	64		T2	530		T4	236
valid_sources[0x59]	48383	1			T1	84		T2	537		T4	223
valid_sources[0x5a]	45230	1			T1	68		T2	505		T4	234
valid_sources[0x5b]	55583	1			T1	68		T2	670		T4	240
valid_sources[0x5c]	53816	1			T1	76		T2	635		T4	257
valid_sources[0x5d]	51966	1			T1	80		T2	650		T4	257
valid_sources[0x5e]	56908	1			T1	81		T2	526		T4	243
valid_sources[0x5f]	54480	1			T1	70		T2	484		T4	243
valid_sources[0x60]	48544	1			T1	67		T2	700		T4	252
valid_sources[0x61]	52373	1			T1	57		T2	655		T4	252
valid_sources[0x62]	75820	1			T1	77		T2	524		T4	270
valid_sources[0x63]	54017	1			T1	78		T2	737		T4	216
valid_sources[0x64]	46439	1			T1	72		T2	554		T4	223
valid_sources[0x65]	47081	1			T1	68		T2	606		T4	256
valid_sources[0x66]	60364	1			T1	69		T2	679		T4	268
valid_sources[0x67]	51349	1			T1	69		T2	645		T4	247
valid_sources[0x68]	51792	1			T1	74		T2	709		T4	239
valid_sources[0x69]	50852	1			T1	81		T2	658		T4	249
valid_sources[0x6a]	51331	1			T1	77		T2	646		T4	218
valid_sources[0x6b]	45685	1			T1	69		T2	676		T4	225
valid_sources[0x6c]	46563	1			T1	66		T2	621		T4	260
valid_sources[0x6d]	48945	1			T1	68		T2	625		T4	243
valid_sources[0x6e]	49166	1			T1	92		T2	515		T4	289
valid_sources[0x6f]	51867	1			T1	62		T2	620		T4	224
valid_sources[0x70]	51246	1			T1	61		T2	625		T4	251
valid_sources[0x71]	49329	1			T1	65		T2	501		T4	246
valid_sources[0x72]	94698	1			T1	69		T2	668		T4	288
valid_sources[0x73]	48552	1			T1	60		T2	694		T4	265
valid_sources[0x74]	48470	1			T1	92		T2	662		T4	242
valid_sources[0x75]	48010	1			T1	66		T2	731		T4	223
valid_sources[0x76]	48144	1			T1	69		T2	574		T4	235
valid_sources[0x77]	71052	1			T1	66		T2	711		T4	254
valid_sources[0x78]	47309	1			T1	70		T2	730		T4	240
valid_sources[0x79]	54176	1			T1	78		T2	722		T4	268
valid_sources[0x7a]	97400	1			T1	78		T2	662		T4	253
valid_sources[0x7b]	56215	1			T1	79		T2	790		T4	245
valid_sources[0x7c]	57736	1			T1	63		T2	509		T4	239
valid_sources[0x7d]	46091	1			T1	60		T2	728		T4	247
valid_sources[0x7e]	46652	1			T1	58		T2	758		T4	257
valid_sources[0x7f]	55393	1			T1	49		T2	701		T4	249
valid_sources[0x80]	53412	1			T1	61		T2	602		T4	206

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3299155

1

T1

6241

T2

32668

T3

196

values[0x0]

all_enables

biggest_size

1772033

1

T1

639

T2

30623

T3

18

values[0x1]

all_enables

biggest_size

1697405

1

T1

509

T2

29846

T3

12

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	229967	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8230995

1

T1

340

T2

155821

T3

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2106957	1			T1	170		T2	39200		T3	10
values[0x0]	3084423	1			T1	90		T2	58383		T3	6
values[0x1]	3269582	1			T1	80		T2	62532		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	83668	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

8377294

1

T1

340

T2

158692

T3

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	32104	1			T2	625		T4	259		T6	8
valid_sources[0x01]	31641	1			T2	584		T4	280		T95	1
valid_sources[0x02]	32998	1			T2	470		T4	302		T14	2
valid_sources[0x03]	33054	1			T2	586		T4	316		T14	1
valid_sources[0x04]	32975	1			T2	703		T3	1		T4	245
valid_sources[0x05]	33024	1			T2	690		T4	242		T14	4
valid_sources[0x06]	32399	1			T2	710		T4	273		T6	1
valid_sources[0x07]	32824	1			T2	647		T4	351		T14	1
valid_sources[0x08]	33512	1			T2	626		T4	224		T8	6
valid_sources[0x09]	32941	1			T2	756		T4	246		T14	4
valid_sources[0x0a]	34176	1			T2	619		T4	327		T14	2
valid_sources[0x0b]	31510	1			T2	483		T4	269		T6	11
valid_sources[0x0c]	33903	1			T2	635		T4	242		T14	6
valid_sources[0x0d]	32460	1			T2	650		T4	315		T10	1
valid_sources[0x0e]	32948	1			T2	549		T4	254		T14	5
valid_sources[0x0f]	34013	1			T2	592		T4	237		T14	2
valid_sources[0x10]	32914	1			T2	569		T4	286		T14	2
valid_sources[0x11]	33220	1			T2	630		T4	216		T14	3
valid_sources[0x12]	33587	1			T2	673		T4	310		T200	1
valid_sources[0x13]	33263	1			T2	645		T4	219		T95	1
valid_sources[0x14]	33164	1			T2	885		T4	232		T6	5
valid_sources[0x15]	32966	1			T2	604		T4	306		T14	7
valid_sources[0x16]	32863	1			T2	678		T4	261		T200	2
valid_sources[0x17]	34378	1			T2	658		T4	356		T6	4
valid_sources[0x18]	32795	1			T2	699		T4	238		T14	1
valid_sources[0x19]	33064	1			T2	689		T4	324		T14	6
valid_sources[0x1a]	33744	1			T2	593		T4	310		T8	1
valid_sources[0x1b]	32056	1			T2	598		T4	226		T14	1
valid_sources[0x1c]	32700	1			T2	534		T4	240		T14	2
valid_sources[0x1d]	33793	1			T2	656		T4	216		T14	3
valid_sources[0x1e]	33131	1			T2	593		T4	257		T14	4
valid_sources[0x1f]	32355	1			T2	656		T4	248		T14	5
valid_sources[0x20]	32701	1			T2	633		T4	314		T14	1
valid_sources[0x21]	33338	1			T2	526		T4	262		T14	1
valid_sources[0x22]	33576	1			T2	679		T4	287		T14	6
valid_sources[0x23]	31795	1			T2	672		T4	234		T14	4
valid_sources[0x24]	32271	1			T2	643		T4	268		T14	4
valid_sources[0x25]	32856	1			T2	593		T4	267		T6	6
valid_sources[0x26]	34011	1			T2	483		T4	313		T14	9
valid_sources[0x27]	32799	1			T2	577		T4	264		T14	1
valid_sources[0x28]	33331	1			T2	727		T4	269		T14	2
valid_sources[0x29]	35574	1			T2	561		T4	197		T14	5
valid_sources[0x2a]	32566	1			T2	621		T4	246		T95	1
valid_sources[0x2b]	32736	1			T2	736		T4	220		T14	6
valid_sources[0x2c]	33003	1			T2	589		T4	251		T14	3
valid_sources[0x2d]	33436	1			T2	849		T4	219		T14	4
valid_sources[0x2e]	33377	1			T2	615		T4	214		T14	1
valid_sources[0x2f]	32463	1			T2	784		T4	293		T14	4
valid_sources[0x30]	31925	1			T2	715		T4	223		T14	1
valid_sources[0x31]	32777	1			T2	553		T4	201		T14	1
valid_sources[0x32]	32850	1			T2	601		T4	231		T14	3
valid_sources[0x33]	33213	1			T2	639		T4	242		T14	9
valid_sources[0x34]	33370	1			T2	651		T4	180		T14	1
valid_sources[0x35]	34095	1			T2	614		T4	201		T6	11
valid_sources[0x36]	34084	1			T2	579		T4	259		T14	7
valid_sources[0x37]	33271	1			T2	615		T4	203		T14	2
valid_sources[0x38]	33082	1			T2	620		T4	210		T14	3
valid_sources[0x39]	33042	1			T2	653		T4	207		T14	1
valid_sources[0x3a]	31951	1			T2	598		T4	284		T10	1
valid_sources[0x3b]	33550	1			T2	847		T4	223		T14	2
valid_sources[0x3c]	32448	1			T2	576		T3	4		T4	301
valid_sources[0x3d]	33135	1			T2	567		T4	283		T14	2
valid_sources[0x3e]	34019	1			T2	579		T4	309		T10	1
valid_sources[0x3f]	32523	1			T2	624		T4	224		T8	5
valid_sources[0x40]	32644	1			T2	660		T4	234		T14	1
valid_sources[0x41]	33438	1			T2	491		T4	234		T12	2
valid_sources[0x42]	32545	1			T2	650		T4	268		T6	8
valid_sources[0x43]	33650	1			T2	790		T4	231		T14	1
valid_sources[0x44]	32206	1			T2	517		T4	239		T6	2
valid_sources[0x45]	32603	1			T2	657		T4	278		T14	3
valid_sources[0x46]	33469	1			T2	636		T4	266		T10	1
valid_sources[0x47]	33723	1			T2	543		T4	249		T12	2
valid_sources[0x48]	32276	1			T2	618		T4	236		T14	4
valid_sources[0x49]	34153	1			T2	656		T4	276		T14	4
valid_sources[0x4a]	32113	1			T2	639		T4	249		T14	1
valid_sources[0x4b]	34215	1			T2	583		T4	306		T153	1
valid_sources[0x4c]	33327	1			T2	590		T4	266		T14	3
valid_sources[0x4d]	32091	1			T2	651		T4	253		T5	140
valid_sources[0x4e]	32933	1			T2	816		T4	264		T8	25
valid_sources[0x4f]	33654	1			T2	585		T4	257		T10	1
valid_sources[0x50]	32392	1			T2	532		T4	283		T10	1
valid_sources[0x51]	32819	1			T2	630		T4	247		T14	1
valid_sources[0x52]	33471	1			T2	598		T4	242		T12	2
valid_sources[0x53]	33524	1			T2	788		T4	348		T10	1
valid_sources[0x54]	33556	1			T2	534		T4	296		T95	2
valid_sources[0x55]	32699	1			T2	583		T4	234		T14	5
valid_sources[0x56]	33117	1			T2	654		T4	258		T14	3
valid_sources[0x57]	33073	1			T2	571		T4	217		T14	2
valid_sources[0x58]	32049	1			T2	671		T4	226		T14	2
valid_sources[0x59]	32853	1			T2	600		T4	236		T14	8
valid_sources[0x5a]	33104	1			T2	677		T4	296		T14	1
valid_sources[0x5b]	32315	1			T2	679		T4	298		T8	13
valid_sources[0x5c]	33252	1			T2	544		T4	254		T14	1
valid_sources[0x5d]	32610	1			T2	584		T4	220		T14	5
valid_sources[0x5e]	32775	1			T2	590		T4	219		T14	1
valid_sources[0x5f]	32261	1			T2	573		T4	213		T14	2
valid_sources[0x60]	33619	1			T2	712		T4	218		T14	2
valid_sources[0x61]	31884	1			T2	631		T4	298		T14	2
valid_sources[0x62]	31718	1			T2	523		T4	224		T14	4
valid_sources[0x63]	33961	1			T2	550		T4	244		T14	4
valid_sources[0x64]	33936	1			T2	532		T4	284		T14	2
valid_sources[0x65]	33321	1			T2	511		T4	296		T6	1
valid_sources[0x66]	33011	1			T2	690		T4	262		T14	3
valid_sources[0x67]	33324	1			T2	605		T4	232		T14	2
valid_sources[0x68]	33034	1			T2	523		T4	260		T14	3
valid_sources[0x69]	33507	1			T2	722		T4	279		T14	3
valid_sources[0x6a]	32228	1			T2	633		T4	317		T200	1
valid_sources[0x6b]	32705	1			T2	614		T4	281		T14	2
valid_sources[0x6c]	34060	1			T2	467		T4	288		T14	1
valid_sources[0x6d]	32856	1			T2	546		T4	199		T10	1
valid_sources[0x6e]	31810	1			T2	705		T4	276		T14	2
valid_sources[0x6f]	33095	1			T2	609		T4	199		T14	3
valid_sources[0x70]	33756	1			T2	608		T4	303		T200	2
valid_sources[0x71]	34038	1			T2	755		T4	295		T14	2
valid_sources[0x72]	32245	1			T2	654		T4	231		T14	6
valid_sources[0x73]	32020	1			T2	578		T4	260		T14	2
valid_sources[0x74]	32093	1			T2	530		T4	235		T6	4
valid_sources[0x75]	33011	1			T2	586		T4	291		T95	1
valid_sources[0x76]	34115	1			T2	662		T4	306		T14	3
valid_sources[0x77]	32710	1			T2	651		T4	312		T14	1
valid_sources[0x78]	32362	1			T2	629		T4	261		T14	1
valid_sources[0x79]	33438	1			T2	679		T4	255		T6	1
valid_sources[0x7a]	33608	1			T2	494		T4	261		T14	1
valid_sources[0x7b]	33899	1			T2	849		T4	306		T14	1
valid_sources[0x7c]	32516	1			T2	631		T4	221		T12	3
valid_sources[0x7d]	32783	1			T2	670		T4	223		T100	1
valid_sources[0x7e]	33034	1			T2	543		T4	234		T10	1
valid_sources[0x7f]	34294	1			T2	699		T4	242		T14	2
valid_sources[0x80]	32589	1			T2	707		T4	219		T14	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2092733

1

T1

170

T2

39165

T3

10

values[0x0]

all_enables

biggest_size

3068858

1

T1

90

T2

58109

T3

6

values[0x1]

all_enables

biggest_size

3069404

1

T1

80

T2

58547

T3

4