Unified Coverage Report :: Module :: prim_arbiter_tree

Module : prim_arbiter_tree

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.91	97.11	80.77			100.00	93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_scrmbl_mtx	79.48	75.00	99.17			100.00	43.75
tb.dut.u_edn_arb	87.74	92.31	65.31			100.00	93.33
tb.dut.u_otp_arb	97.25	98.07	97.16			100.00	93.75
tb.dut.u_otp_ctrl_kdi.u_req_arb	98.34	100.00	99.62			100.00	93.75

Line Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=32,EnDataPort=0,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Line Coverage for Module self-instances :

SCORE	LINE
87.74	92.31

tb.dut.u_edn_arb

	Line No.	Total	Covered	Percent
TOTAL		26	24	92.31
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	1	1
112	2	2
118	2	2
122	0	2
126	2	2
128	2	2
148	1	1
150	1	1
151	1	1
155	1	1
156	1	1
160	1	1
161	1	1
163		unreachable
164	1	1
174	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Line Coverage for Module : prim_arbiter_tree ( parameter N=14,DW=83,EnDataPort=1,IdxW=4,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14,gen_normal_case.gen_tree[3].gen_level[0].Pa=7,gen_normal_case.gen_tree[3].gen_level[0].C0=15,gen_normal_case.gen_tree[3].gen_level[0].C1=16,gen_normal_case.gen_tree[3].gen_level[1].Pa=8,gen_normal_case.gen_tree[3].gen_level[1].C0=17,gen_normal_case.gen_tree[3].gen_level[1].C1=18,gen_normal_case.gen_tree[3].gen_level[2].Pa=9,gen_normal_case.gen_tree[3].gen_level[2].C0=19,gen_normal_case.gen_tree[3].gen_level[2].C1=20,gen_normal_case.gen_tree[3].gen_level[3].Pa=10,gen_normal_case.gen_tree[3].gen_level[3].C0=21,gen_normal_case.gen_tree[3].gen_level[3].C1=22,gen_normal_case.gen_tree[3].gen_level[4].Pa=11,gen_normal_case.gen_tree[3].gen_level[4].C0=23,gen_normal_case.gen_tree[3].gen_level[4].C1=24,gen_normal_case.gen_tree[3].gen_level[5].Pa=12,gen_normal_case.gen_tree[3].gen_level[5].C0=25,gen_normal_case.gen_tree[3].gen_level[5].C1=26,gen_normal_case.gen_tree[3].gen_level[6].Pa=13,gen_normal_case.gen_tree[3].gen_level[6].C0=27,gen_normal_case.gen_tree[3].gen_level[6].C1=28,gen_normal_case.gen_tree[3].gen_level[7].Pa=14,gen_normal_case.gen_tree[3].gen_level[7].C0=29,gen_normal_case.gen_tree[3].gen_level[7].C1=30,gen_normal_case.gen_tree[4].gen_level[0].Pa=15,gen_normal_case.gen_tree[4].gen_level[0].C0=31,gen_normal_case.gen_tree[4].gen_level[0].C1=32,gen_normal_case.gen_tree[4].gen_level[1].Pa=16,gen_normal_case.gen_tree[4].gen_level[1].C0=33,gen_normal_case.gen_tree[4].gen_level[1].C1=34,gen_normal_case.gen_tree[4].gen_level[2].Pa=17,gen_normal_case.gen_tree[4].gen_level[2].C0=35,gen_normal_case.gen_tree[4].gen_level[2].C1=36,gen_normal_case.gen_tree[4].gen_level[3].Pa=18,gen_normal_case.gen_tree[4].gen_level[3].C0=37,gen_normal_case.gen_tree[4].gen_level[3].C1=38,gen_normal_case.gen_tree[4].gen_level[4].Pa=19,gen_normal_case.gen_tree[4].gen_level[4].C0=39,gen_normal_case.gen_tree[4].gen_level[4].C1=40,gen_normal_case.gen_tree[4].gen_level[5].Pa=20,gen_normal_case.gen_tree[4].gen_level[5].C0=41,gen_normal_case.gen_tree[4].gen_level[5].C1=42,gen_normal_case.gen_tree[4].gen_level[6].Pa=21,gen_normal_case.gen_tree[4].gen_level[6].C0=43,gen_normal_case.gen_tree[4].gen_level[6].C1=44,gen_normal_case.gen_tree[4].gen_level[7].Pa=22,gen_normal_case.gen_tree[4].gen_level[7].C0=45,gen_normal_case.gen_tree[4].gen_level[7].C1=46,gen_normal_case.gen_tree[4].gen_level[8].Pa=23,gen_normal_case.gen_tree[4].gen_level[8].C0=47,gen_normal_case.gen_tree[4].gen_level[8].C1=48,gen_normal_case.gen_tree[4].gen_level[9].Pa=24,gen_normal_case.gen_tree[4].gen_level[9].C0=49,gen_normal_case.gen_tree[4].gen_level[9].C1=50,gen_normal_case.gen_tree[4].gen_level[10].Pa=25,gen_normal_case.gen_tree[4].gen_level[10].C0=51,gen_normal_case.gen_tree[4].gen_level[10].C1=52,gen_normal_case.gen_tree[4].gen_level[11].Pa=26,gen_normal_case.gen_tree[4].gen_level[11].C0=53,gen_normal_case.gen_tree[4].gen_level[11].C1=54,gen_normal_case.gen_tree[4].gen_level[12].Pa=27,gen_normal_case.gen_tree[4].gen_level[12].C0=55,gen_normal_case.gen_tree[4].gen_level[12].C1=56,gen_normal_case.gen_tree[4].gen_level[13].Pa=28,gen_normal_case.gen_tree[4].gen_level[13].C0=57,gen_normal_case.gen_tree[4].gen_level[13].C1=58,gen_normal_case.gen_tree[4].gen_level[14].Pa=29,gen_normal_case.gen_tree[4].gen_level[14].C0=59,gen_normal_case.gen_tree[4].gen_level[14].C1=60,gen_normal_case.gen_tree[4].gen_level[15].Pa=30,gen_normal_case.gen_tree[4].gen_level[15].C0=61,gen_normal_case.gen_tree[4].gen_level[15].C1=62 + N=14,DW=72,EnDataPort=1,IdxW=4,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14,gen_normal_case.gen_tree[3].gen_level[0].Pa=7,gen_normal_case.gen_tree[3].gen_level[0].C0=15,gen_normal_case.gen_tree[3].gen_level[0].C1=16,gen_normal_case.gen_tree[3].gen_level[1].Pa=8,gen_normal_case.gen_tree[3].gen_level[1].C0=17,gen_normal_case.gen_tree[3].gen_level[1].C1=18,gen_normal_case.gen_tree[3].gen_level[2].Pa=9,gen_normal_case.gen_tree[3].gen_level[2].C0=19,gen_normal_case.gen_tree[3].gen_level[2].C1=20,gen_normal_case.gen_tree[3].gen_level[3].Pa=10,gen_normal_case.gen_tree[3].gen_level[3].C0=21,gen_normal_case.gen_tree[3].gen_level[3].C1=22,gen_normal_case.gen_tree[3].gen_level[4].Pa=11,gen_normal_case.gen_tree[3].gen_level[4].C0=23,gen_normal_case.gen_tree[3].gen_level[4].C1=24,gen_normal_case.gen_tree[3].gen_level[5].Pa=12,gen_normal_case.gen_tree[3].gen_level[5].C0=25,gen_normal_case.gen_tree[3].gen_level[5].C1=26,gen_normal_case.gen_tree[3].gen_level[6].Pa=13,gen_normal_case.gen_tree[3].gen_level[6].C0=27,gen_normal_case.gen_tree[3].gen_level[6].C1=28,gen_normal_case.gen_tree[3].gen_level[7].Pa=14,gen_normal_case.gen_tree[3].gen_level[7].C0=29,gen_normal_case.gen_tree[3].gen_level[7].C1=30,gen_normal_case.gen_tree[4].gen_level[0].Pa=15,gen_normal_case.gen_tree[4].gen_level[0].C0=31,gen_normal_case.gen_tree[4].gen_level[0].C1=32,gen_normal_case.gen_tree[4].gen_level[1].Pa=16,gen_normal_case.gen_tree[4].gen_level[1].C0=33,gen_normal_case.gen_tree[4].gen_level[1].C1=34,gen_normal_case.gen_tree[4].gen_level[2].Pa=17,gen_normal_case.gen_tree[4].gen_level[2].C0=35,gen_normal_case.gen_tree[4].gen_level[2].C1=36,gen_normal_case.gen_tree[4].gen_level[3].Pa=18,gen_normal_case.gen_tree[4].gen_level[3].C0=37,gen_normal_case.gen_tree[4].gen_level[3].C1=38,gen_normal_case.gen_tree[4].gen_level[4].Pa=19,gen_normal_case.gen_tree[4].gen_level[4].C0=39,gen_normal_case.gen_tree[4].gen_level[4].C1=40,gen_normal_case.gen_tree[4].gen_level[5].Pa=20,gen_normal_case.gen_tree[4].gen_level[5].C0=41,gen_normal_case.gen_tree[4].gen_level[5].C1=42,gen_normal_case.gen_tree[4].gen_level[6].Pa=21,gen_normal_case.gen_tree[4].gen_level[6].C0=43,gen_normal_case.gen_tree[4].gen_level[6].C1=44,gen_normal_case.gen_tree[4].gen_level[7].Pa=22,gen_normal_case.gen_tree[4].gen_level[7].C0=45,gen_normal_case.gen_tree[4].gen_level[7].C1=46,gen_normal_case.gen_tree[4].gen_level[8].Pa=23,gen_normal_case.gen_tree[4].gen_level[8].C0=47,gen_normal_case.gen_tree[4].gen_level[8].C1=48,gen_normal_case.gen_tree[4].gen_level[9].Pa=24,gen_normal_case.gen_tree[4].gen_level[9].C0=49,gen_normal_case.gen_tree[4].gen_level[9].C1=50,gen_normal_case.gen_tree[4].gen_level[10].Pa=25,gen_normal_case.gen_tree[4].gen_level[10].C0=51,gen_normal_case.gen_tree[4].gen_level[10].C1=52,gen_normal_case.gen_tree[4].gen_level[11].Pa=26,gen_normal_case.gen_tree[4].gen_level[11].C0=53,gen_normal_case.gen_tree[4].gen_level[11].C1=54,gen_normal_case.gen_tree[4].gen_level[12].Pa=27,gen_normal_case.gen_tree[4].gen_level[12].C0=55,gen_normal_case.gen_tree[4].gen_level[12].C1=56,gen_normal_case.gen_tree[4].gen_level[13].Pa=28,gen_normal_case.gen_tree[4].gen_level[13].C0=57,gen_normal_case.gen_tree[4].gen_level[13].C1=58,gen_normal_case.gen_tree[4].gen_level[14].Pa=29,gen_normal_case.gen_tree[4].gen_level[14].C0=59,gen_normal_case.gen_tree[4].gen_level[14].C1=60,gen_normal_case.gen_tree[4].gen_level[15].Pa=30,gen_normal_case.gen_tree[4].gen_level[15].C0=61,gen_normal_case.gen_tree[4].gen_level[15].C1=62 )
Line Coverage for Module self-instances :

SCORE	LINE
97.25	98.07

tb.dut.u_otp_arb

SCORE	LINE
79.48	75.00

tb.dut.u_scrmbl_mtx

	Line No.	Total	Covered	Percent
TOTAL		207	205	99.03
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	0	0
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	0	0
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	0	0
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	1	1
112	14	14
118	14	14
122	14	14
126	14	14
128	14	14
138	2	2
148	14	14(1 unreachable)
150	14	14(1 unreachable)
151	14	14(1 unreachable)
155	14	15
156	14	15
160	14	14(1 unreachable)
161	15	15
163	11	11(4 unreachable)
164	15	15
171	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Line Coverage for Module : prim_arbiter_tree ( parameter N=7,DW=264,EnDataPort=1,IdxW=3,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14,gen_normal_case.gen_tree[3].gen_level[0].Pa=7,gen_normal_case.gen_tree[3].gen_level[0].C0=15,gen_normal_case.gen_tree[3].gen_level[0].C1=16,gen_normal_case.gen_tree[3].gen_level[1].Pa=8,gen_normal_case.gen_tree[3].gen_level[1].C0=17,gen_normal_case.gen_tree[3].gen_level[1].C1=18,gen_normal_case.gen_tree[3].gen_level[2].Pa=9,gen_normal_case.gen_tree[3].gen_level[2].C0=19,gen_normal_case.gen_tree[3].gen_level[2].C1=20,gen_normal_case.gen_tree[3].gen_level[3].Pa=10,gen_normal_case.gen_tree[3].gen_level[3].C0=21,gen_normal_case.gen_tree[3].gen_level[3].C1=22,gen_normal_case.gen_tree[3].gen_level[4].Pa=11,gen_normal_case.gen_tree[3].gen_level[4].C0=23,gen_normal_case.gen_tree[3].gen_level[4].C1=24,gen_normal_case.gen_tree[3].gen_level[5].Pa=12,gen_normal_case.gen_tree[3].gen_level[5].C0=25,gen_normal_case.gen_tree[3].gen_level[5].C1=26,gen_normal_case.gen_tree[3].gen_level[6].Pa=13,gen_normal_case.gen_tree[3].gen_level[6].C0=27,gen_normal_case.gen_tree[3].gen_level[6].C1=28,gen_normal_case.gen_tree[3].gen_level[7].Pa=14,gen_normal_case.gen_tree[3].gen_level[7].C0=29,gen_normal_case.gen_tree[3].gen_level[7].C1=30 )
Line Coverage for Module self-instances :

SCORE	LINE
98.34	100.00

tb.dut.u_otp_ctrl_kdi.u_req_arb

	Line No.	Total	Covered	Percent
TOTAL		103	103	100.00
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	7	7
118	7	7
122	7	7
126	7	7
128	7	7
138	1	1
148	7	7
150	7	7
151	7	7
155	7	7
156	7	7
160	7	7
161	7	7
163	4	4(3 unreachable)
164	7	7
171	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=32,EnDataPort=0,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Cond Coverage for Module self-instances :

SCORE	COND
87.74	65.31

tb.dut.u_edn_arb

	Total	Covered	Percent
Conditions	51	32	62.75
Logical	51	32	62.75
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

---

Cond Coverage for Module : prim_arbiter_tree ( parameter N=14,DW=83,EnDataPort=1,IdxW=4,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14,gen_normal_case.gen_tree[3].gen_level[0].Pa=7,gen_normal_case.gen_tree[3].gen_level[0].C0=15,gen_normal_case.gen_tree[3].gen_level[0].C1=16,gen_normal_case.gen_tree[3].gen_level[1].Pa=8,gen_normal_case.gen_tree[3].gen_level[1].C0=17,gen_normal_case.gen_tree[3].gen_level[1].C1=18,gen_normal_case.gen_tree[3].gen_level[2].Pa=9,gen_normal_case.gen_tree[3].gen_level[2].C0=19,gen_normal_case.gen_tree[3].gen_level[2].C1=20,gen_normal_case.gen_tree[3].gen_level[3].Pa=10,gen_normal_case.gen_tree[3].gen_level[3].C0=21,gen_normal_case.gen_tree[3].gen_level[3].C1=22,gen_normal_case.gen_tree[3].gen_level[4].Pa=11,gen_normal_case.gen_tree[3].gen_level[4].C0=23,gen_normal_case.gen_tree[3].gen_level[4].C1=24,gen_normal_case.gen_tree[3].gen_level[5].Pa=12,gen_normal_case.gen_tree[3].gen_level[5].C0=25,gen_normal_case.gen_tree[3].gen_level[5].C1=26,gen_normal_case.gen_tree[3].gen_level[6].Pa=13,gen_normal_case.gen_tree[3].gen_level[6].C0=27,gen_normal_case.gen_tree[3].gen_level[6].C1=28,gen_normal_case.gen_tree[3].gen_level[7].Pa=14,gen_normal_case.gen_tree[3].gen_level[7].C0=29,gen_normal_case.gen_tree[3].gen_level[7].C1=30,gen_normal_case.gen_tree[4].gen_level[0].Pa=15,gen_normal_case.gen_tree[4].gen_level[0].C0=31,gen_normal_case.gen_tree[4].gen_level[0].C1=32,gen_normal_case.gen_tree[4].gen_level[1].Pa=16,gen_normal_case.gen_tree[4].gen_level[1].C0=33,gen_normal_case.gen_tree[4].gen_level[1].C1=34,gen_normal_case.gen_tree[4].gen_level[2].Pa=17,gen_normal_case.gen_tree[4].gen_level[2].C0=35,gen_normal_case.gen_tree[4].gen_level[2].C1=36,gen_normal_case.gen_tree[4].gen_level[3].Pa=18,gen_normal_case.gen_tree[4].gen_level[3].C0=37,gen_normal_case.gen_tree[4].gen_level[3].C1=38,gen_normal_case.gen_tree[4].gen_level[4].Pa=19,gen_normal_case.gen_tree[4].gen_level[4].C0=39,gen_normal_case.gen_tree[4].gen_level[4].C1=40,gen_normal_case.gen_tree[4].gen_level[5].Pa=20,gen_normal_case.gen_tree[4].gen_level[5].C0=41,gen_normal_case.gen_tree[4].gen_level[5].C1=42,gen_normal_case.gen_tree[4].gen_level[6].Pa=21,gen_normal_case.gen_tree[4].gen_level[6].C0=43,gen_normal_case.gen_tree[4].gen_level[6].C1=44,gen_normal_case.gen_tree[4].gen_level[7].Pa=22,gen_normal_case.gen_tree[4].gen_level[7].C0=45,gen_normal_case.gen_tree[4].gen_level[7].C1=46,gen_normal_case.gen_tree[4].gen_level[8].Pa=23,gen_normal_case.gen_tree[4].gen_level[8].C0=47,gen_normal_case.gen_tree[4].gen_level[8].C1=48,gen_normal_case.gen_tree[4].gen_level[9].Pa=24,gen_normal_case.gen_tree[4].gen_level[9].C0=49,gen_normal_case.gen_tree[4].gen_level[9].C1=50,gen_normal_case.gen_tree[4].gen_level[10].Pa=25,gen_normal_case.gen_tree[4].gen_level[10].C0=51,gen_normal_case.gen_tree[4].gen_level[10].C1=52,gen_normal_case.gen_tree[4].gen_level[11].Pa=26,gen_normal_case.gen_tree[4].gen_level[11].C0=53,gen_normal_case.gen_tree[4].gen_level[11].C1=54,gen_normal_case.gen_tree[4].gen_level[12].Pa=27,gen_normal_case.gen_tree[4].gen_level[12].C0=55,gen_normal_case.gen_tree[4].gen_level[12].C1=56,gen_normal_case.gen_tree[4].gen_level[13].Pa=28,gen_normal_case.gen_tree[4].gen_level[13].C0=57,gen_normal_case.gen_tree[4].gen_level[13].C1=58,gen_normal_case.gen_tree[4].gen_level[14].Pa=29,gen_normal_case.gen_tree[4].gen_level[14].C0=59,gen_normal_case.gen_tree[4].gen_level[14].C1=60,gen_normal_case.gen_tree[4].gen_level[15].Pa=30,gen_normal_case.gen_tree[4].gen_level[15].C0=61,gen_normal_case.gen_tree[4].gen_level[15].C1=62 )
Cond Coverage for Module self-instances :

SCORE	COND
97.25	97.16

tb.dut.u_otp_arb

	Total	Covered	Percent
Conditions	559	514	91.95
Logical	559	514	91.95
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
118-155	90.05
155-164	96.82

---

Cond Coverage for Module : prim_arbiter_tree ( parameter N=14,DW=72,EnDataPort=1,IdxW=4,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14,gen_normal_case.gen_tree[3].gen_level[0].Pa=7,gen_normal_case.gen_tree[3].gen_level[0].C0=15,gen_normal_case.gen_tree[3].gen_level[0].C1=16,gen_normal_case.gen_tree[3].gen_level[1].Pa=8,gen_normal_case.gen_tree[3].gen_level[1].C0=17,gen_normal_case.gen_tree[3].gen_level[1].C1=18,gen_normal_case.gen_tree[3].gen_level[2].Pa=9,gen_normal_case.gen_tree[3].gen_level[2].C0=19,gen_normal_case.gen_tree[3].gen_level[2].C1=20,gen_normal_case.gen_tree[3].gen_level[3].Pa=10,gen_normal_case.gen_tree[3].gen_level[3].C0=21,gen_normal_case.gen_tree[3].gen_level[3].C1=22,gen_normal_case.gen_tree[3].gen_level[4].Pa=11,gen_normal_case.gen_tree[3].gen_level[4].C0=23,gen_normal_case.gen_tree[3].gen_level[4].C1=24,gen_normal_case.gen_tree[3].gen_level[5].Pa=12,gen_normal_case.gen_tree[3].gen_level[5].C0=25,gen_normal_case.gen_tree[3].gen_level[5].C1=26,gen_normal_case.gen_tree[3].gen_level[6].Pa=13,gen_normal_case.gen_tree[3].gen_level[6].C0=27,gen_normal_case.gen_tree[3].gen_level[6].C1=28,gen_normal_case.gen_tree[3].gen_level[7].Pa=14,gen_normal_case.gen_tree[3].gen_level[7].C0=29,gen_normal_case.gen_tree[3].gen_level[7].C1=30,gen_normal_case.gen_tree[4].gen_level[0].Pa=15,gen_normal_case.gen_tree[4].gen_level[0].C0=31,gen_normal_case.gen_tree[4].gen_level[0].C1=32,gen_normal_case.gen_tree[4].gen_level[1].Pa=16,gen_normal_case.gen_tree[4].gen_level[1].C0=33,gen_normal_case.gen_tree[4].gen_level[1].C1=34,gen_normal_case.gen_tree[4].gen_level[2].Pa=17,gen_normal_case.gen_tree[4].gen_level[2].C0=35,gen_normal_case.gen_tree[4].gen_level[2].C1=36,gen_normal_case.gen_tree[4].gen_level[3].Pa=18,gen_normal_case.gen_tree[4].gen_level[3].C0=37,gen_normal_case.gen_tree[4].gen_level[3].C1=38,gen_normal_case.gen_tree[4].gen_level[4].Pa=19,gen_normal_case.gen_tree[4].gen_level[4].C0=39,gen_normal_case.gen_tree[4].gen_level[4].C1=40,gen_normal_case.gen_tree[4].gen_level[5].Pa=20,gen_normal_case.gen_tree[4].gen_level[5].C0=41,gen_normal_case.gen_tree[4].gen_level[5].C1=42,gen_normal_case.gen_tree[4].gen_level[6].Pa=21,gen_normal_case.gen_tree[4].gen_level[6].C0=43,gen_normal_case.gen_tree[4].gen_level[6].C1=44,gen_normal_case.gen_tree[4].gen_level[7].Pa=22,gen_normal_case.gen_tree[4].gen_level[7].C0=45,gen_normal_case.gen_tree[4].gen_level[7].C1=46,gen_normal_case.gen_tree[4].gen_level[8].Pa=23,gen_normal_case.gen_tree[4].gen_level[8].C0=47,gen_normal_case.gen_tree[4].gen_level[8].C1=48,gen_normal_case.gen_tree[4].gen_level[9].Pa=24,gen_normal_case.gen_tree[4].gen_level[9].C0=49,gen_normal_case.gen_tree[4].gen_level[9].C1=50,gen_normal_case.gen_tree[4].gen_level[10].Pa=25,gen_normal_case.gen_tree[4].gen_level[10].C0=51,gen_normal_case.gen_tree[4].gen_level[10].C1=52,gen_normal_case.gen_tree[4].gen_level[11].Pa=26,gen_normal_case.gen_tree[4].gen_level[11].C0=53,gen_normal_case.gen_tree[4].gen_level[11].C1=54,gen_normal_case.gen_tree[4].gen_level[12].Pa=27,gen_normal_case.gen_tree[4].gen_level[12].C0=55,gen_normal_case.gen_tree[4].gen_level[12].C1=56,gen_normal_case.gen_tree[4].gen_level[13].Pa=28,gen_normal_case.gen_tree[4].gen_level[13].C0=57,gen_normal_case.gen_tree[4].gen_level[13].C1=58,gen_normal_case.gen_tree[4].gen_level[14].Pa=29,gen_normal_case.gen_tree[4].gen_level[14].C0=59,gen_normal_case.gen_tree[4].gen_level[14].C1=60,gen_normal_case.gen_tree[4].gen_level[15].Pa=30,gen_normal_case.gen_tree[4].gen_level[15].C0=61,gen_normal_case.gen_tree[4].gen_level[15].C1=62 )
Cond Coverage for Module self-instances :

SCORE	COND
79.48	99.17

tb.dut.u_scrmbl_mtx

	Total	Covered	Percent
Conditions	503	359	71.37
Logical	503	359	71.37
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
118-160	70.94
160-164	73.33

---

Cond Coverage for Module : prim_arbiter_tree ( parameter N=7,DW=264,EnDataPort=1,IdxW=3,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14,gen_normal_case.gen_tree[3].gen_level[0].Pa=7,gen_normal_case.gen_tree[3].gen_level[0].C0=15,gen_normal_case.gen_tree[3].gen_level[0].C1=16,gen_normal_case.gen_tree[3].gen_level[1].Pa=8,gen_normal_case.gen_tree[3].gen_level[1].C0=17,gen_normal_case.gen_tree[3].gen_level[1].C1=18,gen_normal_case.gen_tree[3].gen_level[2].Pa=9,gen_normal_case.gen_tree[3].gen_level[2].C0=19,gen_normal_case.gen_tree[3].gen_level[2].C1=20,gen_normal_case.gen_tree[3].gen_level[3].Pa=10,gen_normal_case.gen_tree[3].gen_level[3].C0=21,gen_normal_case.gen_tree[3].gen_level[3].C1=22,gen_normal_case.gen_tree[3].gen_level[4].Pa=11,gen_normal_case.gen_tree[3].gen_level[4].C0=23,gen_normal_case.gen_tree[3].gen_level[4].C1=24,gen_normal_case.gen_tree[3].gen_level[5].Pa=12,gen_normal_case.gen_tree[3].gen_level[5].C0=25,gen_normal_case.gen_tree[3].gen_level[5].C1=26,gen_normal_case.gen_tree[3].gen_level[6].Pa=13,gen_normal_case.gen_tree[3].gen_level[6].C0=27,gen_normal_case.gen_tree[3].gen_level[6].C1=28,gen_normal_case.gen_tree[3].gen_level[7].Pa=14,gen_normal_case.gen_tree[3].gen_level[7].C0=29,gen_normal_case.gen_tree[3].gen_level[7].C1=30 )
Cond Coverage for Module self-instances :

SCORE	COND
98.34	99.62

tb.dut.u_otp_ctrl_kdi.u_req_arb

	Total	Covered	Percent
Conditions	269	261	97.03
Logical	269	261	97.03
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[4] & gen_normal_case.prio_mask_q[4])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[5] & gen_normal_case.prio_mask_q[5])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[6] & gen_normal_case.prio_mask_q[6])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T5,T10,T14
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T5,T10
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T5,T10
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T5,T10
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[4] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T5,T14,T12
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[5] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T97,T15,T150
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[6] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T10,T11,T194
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[4])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[5])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[6])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T14
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T5,T10,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T10
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T91,T246,T247
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])

-1-	-2-	Status	Tests
0	1	Covered	T11,T208,T90
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T10
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[1].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T10
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[1].C1])

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[2].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T208,T18,T19
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[2].C1])

-1-	-2-	Status	Tests
0	1	Covered	T11,T90,T132
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[3].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[3].C1])

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Unreachable

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[2].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[2].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[3].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[3].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[2].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[3].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[2].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[3].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[2].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[3].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T10,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T10,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T10,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T10,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T208
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_tree ( parameter N=14,DW=83,EnDataPort=1,IdxW=4,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14,gen_normal_case.gen_tree[3].gen_level[0].Pa=7,gen_normal_case.gen_tree[3].gen_level[0].C0=15,gen_normal_case.gen_tree[3].gen_level[0].C1=16,gen_normal_case.gen_tree[3].gen_level[1].Pa=8,gen_normal_case.gen_tree[3].gen_level[1].C0=17,gen_normal_case.gen_tree[3].gen_level[1].C1=18,gen_normal_case.gen_tree[3].gen_level[2].Pa=9,gen_normal_case.gen_tree[3].gen_level[2].C0=19,gen_normal_case.gen_tree[3].gen_level[2].C1=20,gen_normal_case.gen_tree[3].gen_level[3].Pa=10,gen_normal_case.gen_tree[3].gen_level[3].C0=21,gen_normal_case.gen_tree[3].gen_level[3].C1=22,gen_normal_case.gen_tree[3].gen_level[4].Pa=11,gen_normal_case.gen_tree[3].gen_level[4].C0=23,gen_normal_case.gen_tree[3].gen_level[4].C1=24,gen_normal_case.gen_tree[3].gen_level[5].Pa=12,gen_normal_case.gen_tree[3].gen_level[5].C0=25,gen_normal_case.gen_tree[3].gen_level[5].C1=26,gen_normal_case.gen_tree[3].gen_level[6].Pa=13,gen_normal_case.gen_tree[3].gen_level[6].C0=27,gen_normal_case.gen_tree[3].gen_level[6].C1=28,gen_normal_case.gen_tree[3].gen_level[7].Pa=14,gen_normal_case.gen_tree[3].gen_level[7].C0=29,gen_normal_case.gen_tree[3].gen_level[7].C1=30,gen_normal_case.gen_tree[4].gen_level[0].Pa=15,gen_normal_case.gen_tree[4].gen_level[0].C0=31,gen_normal_case.gen_tree[4].gen_level[0].C1=32,gen_normal_case.gen_tree[4].gen_level[1].Pa=16,gen_normal_case.gen_tree[4].gen_level[1].C0=33,gen_normal_case.gen_tree[4].gen_level[1].C1=34,gen_normal_case.gen_tree[4].gen_level[2].Pa=17,gen_normal_case.gen_tree[4].gen_level[2].C0=35,gen_normal_case.gen_tree[4].gen_level[2].C1=36,gen_normal_case.gen_tree[4].gen_level[3].Pa=18,gen_normal_case.gen_tree[4].gen_level[3].C0=37,gen_normal_case.gen_tree[4].gen_level[3].C1=38,gen_normal_case.gen_tree[4].gen_level[4].Pa=19,gen_normal_case.gen_tree[4].gen_level[4].C0=39,gen_normal_case.gen_tree[4].gen_level[4].C1=40,gen_normal_case.gen_tree[4].gen_level[5].Pa=20,gen_normal_case.gen_tree[4].gen_level[5].C0=41,gen_normal_case.gen_tree[4].gen_level[5].C1=42,gen_normal_case.gen_tree[4].gen_level[6].Pa=21,gen_normal_case.gen_tree[4].gen_level[6].C0=43,gen_normal_case.gen_tree[4].gen_level[6].C1=44,gen_normal_case.gen_tree[4].gen_level[7].Pa=22,gen_normal_case.gen_tree[4].gen_level[7].C0=45,gen_normal_case.gen_tree[4].gen_level[7].C1=46,gen_normal_case.gen_tree[4].gen_level[8].Pa=23,gen_normal_case.gen_tree[4].gen_level[8].C0=47,gen_normal_case.gen_tree[4].gen_level[8].C1=48,gen_normal_case.gen_tree[4].gen_level[9].Pa=24,gen_normal_case.gen_tree[4].gen_level[9].C0=49,gen_normal_case.gen_tree[4].gen_level[9].C1=50,gen_normal_case.gen_tree[4].gen_level[10].Pa=25,gen_normal_case.gen_tree[4].gen_level[10].C0=51,gen_normal_case.gen_tree[4].gen_level[10].C1=52,gen_normal_case.gen_tree[4].gen_level[11].Pa=26,gen_normal_case.gen_tree[4].gen_level[11].C0=53,gen_normal_case.gen_tree[4].gen_level[11].C1=54,gen_normal_case.gen_tree[4].gen_level[12].Pa=27,gen_normal_case.gen_tree[4].gen_level[12].C0=55,gen_normal_case.gen_tree[4].gen_level[12].C1=56,gen_normal_case.gen_tree[4].gen_level[13].Pa=28,gen_normal_case.gen_tree[4].gen_level[13].C0=57,gen_normal_case.gen_tree[4].gen_level[13].C1=58,gen_normal_case.gen_tree[4].gen_level[14].Pa=29,gen_normal_case.gen_tree[4].gen_level[14].C0=59,gen_normal_case.gen_tree[4].gen_level[14].C1=60,gen_normal_case.gen_tree[4].gen_level[15].Pa=30,gen_normal_case.gen_tree[4].gen_level[15].C0=61,gen_normal_case.gen_tree[4].gen_level[15].C1=62 + N=14,DW=72,EnDataPort=1,IdxW=4,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14,gen_normal_case.gen_tree[3].gen_level[0].Pa=7,gen_normal_case.gen_tree[3].gen_level[0].C0=15,gen_normal_case.gen_tree[3].gen_level[0].C1=16,gen_normal_case.gen_tree[3].gen_level[1].Pa=8,gen_normal_case.gen_tree[3].gen_level[1].C0=17,gen_normal_case.gen_tree[3].gen_level[1].C1=18,gen_normal_case.gen_tree[3].gen_level[2].Pa=9,gen_normal_case.gen_tree[3].gen_level[2].C0=19,gen_normal_case.gen_tree[3].gen_level[2].C1=20,gen_normal_case.gen_tree[3].gen_level[3].Pa=10,gen_normal_case.gen_tree[3].gen_level[3].C0=21,gen_normal_case.gen_tree[3].gen_level[3].C1=22,gen_normal_case.gen_tree[3].gen_level[4].Pa=11,gen_normal_case.gen_tree[3].gen_level[4].C0=23,gen_normal_case.gen_tree[3].gen_level[4].C1=24,gen_normal_case.gen_tree[3].gen_level[5].Pa=12,gen_normal_case.gen_tree[3].gen_level[5].C0=25,gen_normal_case.gen_tree[3].gen_level[5].C1=26,gen_normal_case.gen_tree[3].gen_level[6].Pa=13,gen_normal_case.gen_tree[3].gen_level[6].C0=27,gen_normal_case.gen_tree[3].gen_level[6].C1=28,gen_normal_case.gen_tree[3].gen_level[7].Pa=14,gen_normal_case.gen_tree[3].gen_level[7].C0=29,gen_normal_case.gen_tree[3].gen_level[7].C1=30,gen_normal_case.gen_tree[4].gen_level[0].Pa=15,gen_normal_case.gen_tree[4].gen_level[0].C0=31,gen_normal_case.gen_tree[4].gen_level[0].C1=32,gen_normal_case.gen_tree[4].gen_level[1].Pa=16,gen_normal_case.gen_tree[4].gen_level[1].C0=33,gen_normal_case.gen_tree[4].gen_level[1].C1=34,gen_normal_case.gen_tree[4].gen_level[2].Pa=17,gen_normal_case.gen_tree[4].gen_level[2].C0=35,gen_normal_case.gen_tree[4].gen_level[2].C1=36,gen_normal_case.gen_tree[4].gen_level[3].Pa=18,gen_normal_case.gen_tree[4].gen_level[3].C0=37,gen_normal_case.gen_tree[4].gen_level[3].C1=38,gen_normal_case.gen_tree[4].gen_level[4].Pa=19,gen_normal_case.gen_tree[4].gen_level[4].C0=39,gen_normal_case.gen_tree[4].gen_level[4].C1=40,gen_normal_case.gen_tree[4].gen_level[5].Pa=20,gen_normal_case.gen_tree[4].gen_level[5].C0=41,gen_normal_case.gen_tree[4].gen_level[5].C1=42,gen_normal_case.gen_tree[4].gen_level[6].Pa=21,gen_normal_case.gen_tree[4].gen_level[6].C0=43,gen_normal_case.gen_tree[4].gen_level[6].C1=44,gen_normal_case.gen_tree[4].gen_level[7].Pa=22,gen_normal_case.gen_tree[4].gen_level[7].C0=45,gen_normal_case.gen_tree[4].gen_level[7].C1=46,gen_normal_case.gen_tree[4].gen_level[8].Pa=23,gen_normal_case.gen_tree[4].gen_level[8].C0=47,gen_normal_case.gen_tree[4].gen_level[8].C1=48,gen_normal_case.gen_tree[4].gen_level[9].Pa=24,gen_normal_case.gen_tree[4].gen_level[9].C0=49,gen_normal_case.gen_tree[4].gen_level[9].C1=50,gen_normal_case.gen_tree[4].gen_level[10].Pa=25,gen_normal_case.gen_tree[4].gen_level[10].C0=51,gen_normal_case.gen_tree[4].gen_level[10].C1=52,gen_normal_case.gen_tree[4].gen_level[11].Pa=26,gen_normal_case.gen_tree[4].gen_level[11].C0=53,gen_normal_case.gen_tree[4].gen_level[11].C1=54,gen_normal_case.gen_tree[4].gen_level[12].Pa=27,gen_normal_case.gen_tree[4].gen_level[12].C0=55,gen_normal_case.gen_tree[4].gen_level[12].C1=56,gen_normal_case.gen_tree[4].gen_level[13].Pa=28,gen_normal_case.gen_tree[4].gen_level[13].C0=57,gen_normal_case.gen_tree[4].gen_level[13].C1=58,gen_normal_case.gen_tree[4].gen_level[14].Pa=29,gen_normal_case.gen_tree[4].gen_level[14].C0=59,gen_normal_case.gen_tree[4].gen_level[14].C1=60,gen_normal_case.gen_tree[4].gen_level[15].Pa=30,gen_normal_case.gen_tree[4].gen_level[15].C0=61,gen_normal_case.gen_tree[4].gen_level[15].C1=62 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
97.25	100.00

tb.dut.u_otp_arb

SCORE	BRANCH
79.48	100.00

tb.dut.u_scrmbl_mtx

	Line No.	Total	Covered	Percent
Branches		88	88	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	1	1	100.00
TERNARY	156	1	1	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=32,EnDataPort=0,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
87.74	100.00

tb.dut.u_edn_arb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_tree ( parameter N=7,DW=264,EnDataPort=1,IdxW=3,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14,gen_normal_case.gen_tree[3].gen_level[0].Pa=7,gen_normal_case.gen_tree[3].gen_level[0].C0=15,gen_normal_case.gen_tree[3].gen_level[0].C1=16,gen_normal_case.gen_tree[3].gen_level[1].Pa=8,gen_normal_case.gen_tree[3].gen_level[1].C0=17,gen_normal_case.gen_tree[3].gen_level[1].C1=18,gen_normal_case.gen_tree[3].gen_level[2].Pa=9,gen_normal_case.gen_tree[3].gen_level[2].C0=19,gen_normal_case.gen_tree[3].gen_level[2].C1=20,gen_normal_case.gen_tree[3].gen_level[3].Pa=10,gen_normal_case.gen_tree[3].gen_level[3].C0=21,gen_normal_case.gen_tree[3].gen_level[3].C1=22,gen_normal_case.gen_tree[3].gen_level[4].Pa=11,gen_normal_case.gen_tree[3].gen_level[4].C0=23,gen_normal_case.gen_tree[3].gen_level[4].C1=24,gen_normal_case.gen_tree[3].gen_level[5].Pa=12,gen_normal_case.gen_tree[3].gen_level[5].C0=25,gen_normal_case.gen_tree[3].gen_level[5].C1=26,gen_normal_case.gen_tree[3].gen_level[6].Pa=13,gen_normal_case.gen_tree[3].gen_level[6].C0=27,gen_normal_case.gen_tree[3].gen_level[6].C1=28,gen_normal_case.gen_tree[3].gen_level[7].Pa=14,gen_normal_case.gen_tree[3].gen_level[7].C0=29,gen_normal_case.gen_tree[3].gen_level[7].C1=30 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.34	100.00

tb.dut.u_otp_ctrl_kdi.u_req_arb

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_tree

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1744370248	1740886604	0	0
CheckNGreaterZero_A	4580	4580	0	0
GntImpliesReady_A	1744370248	1791509	0	0
GntImpliesValid_A	1744370248	1791509	0	0
GrantKnown_A	1744370248	1740886604	0	0
IdxKnown_A	1744370248	1740886604	0	0
IndexIsCorrect_A	1744370248	1791509	0	0
LockArbDecision_A	1744370248	80446953	0	0
NoReadyValidNoGrant_A	1744370248	1196731262	0	0
ReadyAndValidImplyGrant_A	1744370248	1791509	0	0
ReqAndReadyImplyGrant_A	1744370248	1791509	0	0
ReqImpliesValid_A	1744370248	125523852	0	0
ReqStaysHighUntilGranted0_M	1744370248	80446953	0	0
RoundRobin_A	1744370248	0	0	4580
ValidKnown_A	1744370248	1740886604	0	0
gen_data_port_assertion.DataFlow_A	1308277686	1517008	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1744370248	1740886604	0	0
T1	2224172	2215952	0	0
T2	2364128	2364068	0	0
T3	40476	39392	0	0
T4	832412	832368	0	0
T5	162420	158332	0	0
T6	235388	231496	0	0
T7	39388	38288	0	0
T8	192440	189576	0	0
T9	53312	52656	0	0
T10	80384	79648	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4580	4580	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1744370248	1791509	0	0
T1	1668129	13173	0	0
T2	1773096	5532	0	0
T3	30357	245	0	0
T4	624309	4464	0	0
T5	121815	1425	0	0
T6	176541	1077	0	0
T7	29541	174	0	0
T8	144330	1026	0	0
T9	39984	239	0	0
T10	60288	633	0	0
T14	0	1427	0	0
T96	0	85	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1744370248	1791509	0	0
T1	1668129	13173	0	0
T2	1773096	5532	0	0
T3	30357	245	0	0
T4	624309	4464	0	0
T5	121815	1425	0	0
T6	176541	1077	0	0
T7	29541	174	0	0
T8	144330	1026	0	0
T9	39984	239	0	0
T10	60288	633	0	0
T14	0	1427	0	0
T96	0	85	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1744370248	1740886604	0	0
T1	2224172	2215952	0	0
T2	2364128	2364068	0	0
T3	40476	39392	0	0
T4	832412	832368	0	0
T5	162420	158332	0	0
T6	235388	231496	0	0
T7	39388	38288	0	0
T8	192440	189576	0	0
T9	53312	52656	0	0
T10	80384	79648	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1744370248	1740886604	0	0
T1	2224172	2215952	0	0
T2	2364128	2364068	0	0
T3	40476	39392	0	0
T4	832412	832368	0	0
T5	162420	158332	0	0
T6	235388	231496	0	0
T7	39388	38288	0	0
T8	192440	189576	0	0
T9	53312	52656	0	0
T10	80384	79648	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1744370248	1791509	0	0
T1	1668129	13173	0	0
T2	1773096	5532	0	0
T3	30357	245	0	0
T4	624309	4464	0	0
T5	121815	1425	0	0
T6	176541	1077	0	0
T7	29541	174	0	0
T8	144330	1026	0	0
T9	39984	239	0	0
T10	60288	633	0	0
T14	0	1427	0	0
T96	0	85	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1744370248	80446953	0	0
T1	1668129	730722	0	0
T2	1773096	176020	0	0
T3	30357	3184	0	0
T4	624309	39070	0	0
T5	121815	42134	0	0
T6	176541	23873	0	0
T7	29541	1372	0	0
T8	144330	18327	0	0
T9	39984	1248	0	0
T10	60288	19876	0	0
T14	0	111179	0	0
T96	0	15239	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1744370248	1196731262	0	0
T1	2224172	728573	0	0
T2	2364128	1782540	0	0
T3	40476	22200	0	0
T4	832412	637081	0	0
T5	162420	58032	0	0
T6	235388	130989	0	0
T7	39388	25314	0	0
T8	192440	105242	0	0
T9	53312	35604	0	0
T10	80384	26885	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1744370248	1791509	0	0
T1	1668129	13173	0	0
T2	1773096	5532	0	0
T3	30357	245	0	0
T4	624309	4464	0	0
T5	121815	1425	0	0
T6	176541	1077	0	0
T7	29541	174	0	0
T8	144330	1026	0	0
T9	39984	239	0	0
T10	60288	633	0	0
T14	0	1427	0	0
T96	0	85	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1744370248	1791509	0	0
T1	1668129	13173	0	0
T2	1773096	5532	0	0
T3	30357	245	0	0
T4	624309	4464	0	0
T5	121815	1425	0	0
T6	176541	1077	0	0
T7	29541	174	0	0
T8	144330	1026	0	0
T9	39984	239	0	0
T10	60288	633	0	0
T14	0	1427	0	0
T96	0	85	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1744370248	125523852	0	0
T1	2224172	1027691	0	0
T2	2364128	287517	0	0
T3	40476	9952	0	0
T4	832412	89964	0	0
T5	162420	75530	0	0
T6	235388	55663	0	0
T7	39388	6081	0	0
T8	192440	46543	0	0
T9	53312	7496	0	0
T10	80384	36797	0	0
T14	0	112623	0	0
T96	0	15324	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1744370248	80446953	0	0
T1	1668129	730722	0	0
T2	1773096	176020	0	0
T3	30357	3184	0	0
T4	624309	39070	0	0
T5	121815	42134	0	0
T6	176541	23873	0	0
T7	29541	1372	0	0
T8	144330	18327	0	0
T9	39984	1248	0	0
T10	60288	19876	0	0
T14	0	111179	0	0
T96	0	15239	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1744370248	0	0	4580

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1744370248	1740886604	0	0
T1	2224172	2215952	0	0
T2	2364128	2364068	0	0
T3	40476	39392	0	0
T4	832412	832368	0	0
T5	162420	158332	0	0
T6	235388	231496	0	0
T7	39388	38288	0	0
T8	192440	189576	0	0
T9	53312	52656	0	0
T10	80384	79648	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1308277686	1517008	0	0
T1	1112086	12909	0	0
T2	1182064	4703	0	0
T3	20238	197	0	0
T4	416206	4001	0	0
T5	81210	1180	0	0
T6	117694	948	0	0
T7	19694	174	0	0
T8	96220	749	0	0
T9	26656	239	0	0
T10	40192	315	0	0
T14	0	183	0	0
T96	0	14	0	0