Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : otp_ctrl_prim_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.49 100.00 97.98 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_prim_reg_top_1.0/rtl/otp_ctrl_prim_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.32 91.84 99.74 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.45 97.27 100.00 100.00 100.00 100.00 gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_chk 100.00 100.00 100.00 100.00
u_csr0_field0 100.00 100.00 100.00 100.00
u_csr0_field1 100.00 100.00 100.00 100.00
u_csr0_field2 100.00 100.00 100.00 100.00
u_csr0_field3 100.00 100.00 100.00 100.00
u_csr0_field4 100.00 100.00 100.00 100.00
u_csr1_field0 100.00 100.00 100.00 100.00
u_csr1_field1 100.00 100.00 100.00 100.00
u_csr1_field2 100.00 100.00 100.00 100.00
u_csr1_field3 100.00 100.00 100.00 100.00
u_csr1_field4 100.00 100.00 100.00 100.00
u_csr2 100.00 100.00 100.00 100.00
u_csr3_field0 100.00 100.00 100.00 100.00
u_csr3_field1 100.00 100.00 100.00 100.00
u_csr3_field2 100.00 100.00 100.00 100.00
u_csr3_field3 87.50 62.50 100.00 100.00
u_csr3_field4 87.50 62.50 100.00 100.00
u_csr3_field5 87.50 62.50 100.00 100.00
u_csr3_field6 87.50 62.50 100.00 100.00
u_csr3_field7 87.50 62.50 100.00 100.00
u_csr3_field8 87.50 62.50 100.00 100.00
u_csr4_field0 100.00 100.00 100.00 100.00
u_csr4_field1 100.00 100.00 100.00 100.00
u_csr4_field2 100.00 100.00 100.00 100.00
u_csr4_field3 100.00 100.00 100.00 100.00
u_csr5_field0 100.00 100.00 100.00 100.00
u_csr5_field1 100.00 100.00 100.00 100.00
u_csr5_field2 87.50 62.50 100.00 100.00
u_csr5_field3 87.50 62.50 100.00 100.00
u_csr5_field4 87.50 62.50 100.00 100.00
u_csr5_field5 87.50 62.50 100.00 100.00
u_csr5_field6 100.00 100.00 100.00 100.00
u_csr6_field0 100.00 100.00 100.00 100.00
u_csr6_field1 100.00 100.00 100.00 100.00
u_csr6_field2 100.00 100.00 100.00 100.00
u_csr6_field3 100.00 100.00 100.00 100.00
u_csr7_field0 87.50 62.50 100.00 100.00
u_csr7_field1 87.50 62.50 100.00 100.00
u_csr7_field2 87.50 62.50 100.00 100.00
u_csr7_field3 87.50 62.50 100.00 100.00
u_prim_reg_we_check 100.00 100.00 100.00
u_reg_if 98.97 97.14 98.75 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00

Line Coverage for Module : otp_ctrl_prim_reg_top
Line No.TotalCoveredPercent
TOTAL104104100.00
ALWAYS6844100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
ALWAYS126899100.00
CONT_ASSIGN127911100.00
ALWAYS128311100.00
CONT_ASSIGN129511100.00
CONT_ASSIGN129711100.00
CONT_ASSIGN129911100.00
CONT_ASSIGN130111100.00
CONT_ASSIGN130311100.00
CONT_ASSIGN130511100.00
CONT_ASSIGN130611100.00
CONT_ASSIGN130811100.00
CONT_ASSIGN131011100.00
CONT_ASSIGN131211100.00
CONT_ASSIGN131411100.00
CONT_ASSIGN131611100.00
CONT_ASSIGN131711100.00
CONT_ASSIGN131911100.00
CONT_ASSIGN132011100.00
CONT_ASSIGN132211100.00
CONT_ASSIGN132411100.00
CONT_ASSIGN132611100.00
CONT_ASSIGN132711100.00
CONT_ASSIGN132911100.00
CONT_ASSIGN133111100.00
CONT_ASSIGN133311100.00
CONT_ASSIGN133511100.00
CONT_ASSIGN133611100.00
CONT_ASSIGN133811100.00
CONT_ASSIGN134011100.00
CONT_ASSIGN134211100.00
CONT_ASSIGN134311100.00
CONT_ASSIGN134511100.00
CONT_ASSIGN134711100.00
CONT_ASSIGN134911100.00
CONT_ASSIGN135111100.00
ALWAYS135599100.00
ALWAYS13684141100.00
CONT_ASSIGN144400
CONT_ASSIGN145211100.00
CONT_ASSIGN145311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_prim_reg_top_1.0/rtl/otp_ctrl_prim_reg_top.sv' or '../src/lowrisc_ip_otp_ctrl_prim_reg_top_1.0/rtl/otp_ctrl_prim_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
77 1 1
89 1 1
90 1 1
118 1 1
119 1 1
1268 1 1
1269 1 1
1270 1 1
1271 1 1
1272 1 1
1273 1 1
1274 1 1
1275 1 1
1276 1 1
1279 1 1
1283 1 1
1295 1 1
1297 1 1
1299 1 1
1301 1 1
1303 1 1
1305 1 1
1306 1 1
1308 1 1
1310 1 1
1312 1 1
1314 1 1
1316 1 1
1317 1 1
1319 1 1
1320 1 1
1322 1 1
1324 1 1
1326 1 1
1327 1 1
1329 1 1
1331 1 1
1333 1 1
1335 1 1
1336 1 1
1338 1 1
1340 1 1
1342 1 1
1343 1 1
1345 1 1
1347 1 1
1349 1 1
1351 1 1
1355 1 1
1356 1 1
1357 1 1
1358 1 1
1359 1 1
1360 1 1
1361 1 1
1362 1 1
1363 1 1
1368 1 1
1369 1 1
1371 1 1
1372 1 1
1373 1 1
1374 1 1
1375 1 1
1379 1 1
1380 1 1
1381 1 1
1382 1 1
1383 1 1
1387 1 1
1391 1 1
1392 1 1
1393 1 1
1394 1 1
1395 1 1
1396 1 1
1397 1 1
1398 1 1
1399 1 1
1403 1 1
1404 1 1
1405 1 1
1406 1 1
1410 1 1
1411 1 1
1412 1 1
1413 1 1
1414 1 1
1415 1 1
1416 1 1
1420 1 1
1421 1 1
1422 1 1
1423 1 1
1427 1 1
1428 1 1
1429 1 1
1430 1 1
1444 unreachable
1452 1 1
1453 1 1


Cond Coverage for Module : otp_ctrl_prim_reg_top
TotalCoveredPercent
Conditions999797.98
Logical999797.98
Non-Logical00
Event00

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T4,T14

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T18,T19
10CoveredT256,T257,T258

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT17,T18,T19
010CoveredT256,T257,T258
100CoveredT17,T18,T19

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT256,T257,T258
010CoveredT2,T4,T11
100Not Covered

 LINE       1269
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR0_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT2,T4,T14
1CoveredT1,T2,T4

 LINE       1270
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR1_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT2,T4,T14

 LINE       1271
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR2_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT2,T4,T14

 LINE       1272
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR3_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT2,T4,T14

 LINE       1273
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR4_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT2,T4,T14

 LINE       1274
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR5_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT2,T4,T14

 LINE       1275
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR6_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT2,T4,T14

 LINE       1276
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR7_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT2,T4,T14

 LINE       1279
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T14

 LINE       1279
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T14
10CoveredT2,T4,T14

 LINE       1283
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[4] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T14,T12
11CoveredT2,T4,T11

 LINE       1283
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1111 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1111 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b0111 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b0011 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0011 & (~reg_be))))))
-1--2--3--4--5--6--7--8-StatusTests
00000000CoveredT2,T4,T14
00000001CoveredT2,T4,T12
00000010CoveredT2,T4,T12
00000100CoveredT2,T4,T12
00001000CoveredT2,T4,T12
00010000CoveredT2,T4,T12
00100000CoveredT2,T4,T12
01000000CoveredT2,T4,T12
10000000CoveredT1,T2,T3

 LINE       1283
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT2,T4,T12
10CoveredT2,T4,T14
11CoveredT1,T2,T3

 LINE       1283
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T4,T14
11CoveredT2,T4,T12

 LINE       1283
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T4,T14
11CoveredT2,T4,T12

 LINE       1283
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T4,T14
11CoveredT2,T4,T12

 LINE       1283
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T4,T14
11CoveredT2,T4,T12

 LINE       1283
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T4,T14
11CoveredT2,T4,T12

 LINE       1283
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T4,T14
11CoveredT2,T4,T12

 LINE       1283
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T4,T14
11CoveredT2,T4,T12

 LINE       1295
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT2,T14,T12
101CoveredT1,T2,T3
110CoveredT2,T4,T132
111CoveredT2,T14,T12

 LINE       1306
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT2,T14,T12
101CoveredT2,T4,T14
110CoveredT2,T4,T11
111CoveredT2,T14,T12

 LINE       1317
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT2,T14,T12
101CoveredT2,T4,T14
110CoveredT2,T4,T11
111CoveredT2,T14,T12

 LINE       1320
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT2,T14,T12
101CoveredT2,T4,T14
110CoveredT2,T4,T11
111CoveredT2,T14,T12

 LINE       1327
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT2,T14,T12
101CoveredT2,T4,T14
110CoveredT2,T4,T132
111CoveredT2,T14,T12

 LINE       1336
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT2,T14,T12
101CoveredT2,T4,T14
110CoveredT2,T4,T11
111CoveredT2,T14,T12

 LINE       1343
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT2,T14,T12
101CoveredT2,T4,T14
110CoveredT2,T4,T132
111CoveredT2,T14,T12

Branch Coverage for Module : otp_ctrl_prim_reg_top
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 1279 2 2 100.00
IF 68 3 3 100.00
CASE 1369 9 9 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_prim_reg_top_1.0/rtl/otp_ctrl_prim_reg_top.sv' or '../src/lowrisc_ip_otp_ctrl_prim_reg_top_1.0/rtl/otp_ctrl_prim_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 1279 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T2,T4,T14
0 Covered T1,T2,T3


LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T17,T18,T19
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 1369 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T2,T3
addr_hit[1] Covered T2,T4,T14
addr_hit[2] Covered T2,T4,T14
addr_hit[3] Covered T2,T4,T14
addr_hit[4] Covered T2,T4,T14
addr_hit[5] Covered T2,T4,T14
addr_hit[6] Covered T2,T4,T14
addr_hit[7] Covered T2,T4,T14
default Covered T2,T4,T14


Assert Coverage for Module : otp_ctrl_prim_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
en2addrHit 439258479 92331 0 0
reAfterRv 439258479 92331 0 0
rePulse 439258479 27546 0 0
wePulse 439258479 64785 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 439258479 92331 0 0
T2 591032 2841 0 0
T3 10119 0 0 0
T4 208103 749 0 0
T5 40605 0 0 0
T6 58847 0 0 0
T7 9847 0 0 0
T8 48110 0 0 0
T9 13328 0 0 0
T10 20096 0 0 0
T11 0 76 0 0
T12 0 48 0 0
T14 215520 22 0 0
T31 0 80 0 0
T55 0 30 0 0
T90 0 206 0 0
T103 0 8 0 0
T223 0 40 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 439258479 92331 0 0
T2 591032 2841 0 0
T3 10119 0 0 0
T4 208103 749 0 0
T5 40605 0 0 0
T6 58847 0 0 0
T7 9847 0 0 0
T8 48110 0 0 0
T9 13328 0 0 0
T10 20096 0 0 0
T11 0 76 0 0
T12 0 48 0 0
T14 215520 22 0 0
T31 0 80 0 0
T55 0 30 0 0
T90 0 206 0 0
T103 0 8 0 0
T223 0 40 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 439258479 27546 0 0
T2 591032 169 0 0
T3 10119 0 0 0
T4 208103 39 0 0
T5 40605 0 0 0
T6 58847 0 0 0
T7 9847 0 0 0
T8 48110 0 0 0
T9 13328 0 0 0
T10 20096 0 0 0
T11 0 72 0 0
T12 0 24 0 0
T14 215520 11 0 0
T31 0 80 0 0
T55 0 15 0 0
T90 0 103 0 0
T103 0 4 0 0
T223 0 40 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 439258479 64785 0 0
T2 591032 2672 0 0
T3 10119 0 0 0
T4 208103 710 0 0
T5 40605 0 0 0
T6 58847 0 0 0
T7 9847 0 0 0
T8 48110 0 0 0
T9 13328 0 0 0
T10 20096 0 0 0
T11 0 4 0 0
T12 0 24 0 0
T14 215520 11 0 0
T55 0 15 0 0
T90 0 103 0 0
T93 0 104 0 0
T103 0 4 0 0
T132 0 179 0 0

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top
Line No.TotalCoveredPercent
TOTAL104104100.00
ALWAYS6844100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
ALWAYS126899100.00
CONT_ASSIGN127911100.00
ALWAYS128311100.00
CONT_ASSIGN129511100.00
CONT_ASSIGN129711100.00
CONT_ASSIGN129911100.00
CONT_ASSIGN130111100.00
CONT_ASSIGN130311100.00
CONT_ASSIGN130511100.00
CONT_ASSIGN130611100.00
CONT_ASSIGN130811100.00
CONT_ASSIGN131011100.00
CONT_ASSIGN131211100.00
CONT_ASSIGN131411100.00
CONT_ASSIGN131611100.00
CONT_ASSIGN131711100.00
CONT_ASSIGN131911100.00
CONT_ASSIGN132011100.00
CONT_ASSIGN132211100.00
CONT_ASSIGN132411100.00
CONT_ASSIGN132611100.00
CONT_ASSIGN132711100.00
CONT_ASSIGN132911100.00
CONT_ASSIGN133111100.00
CONT_ASSIGN133311100.00
CONT_ASSIGN133511100.00
CONT_ASSIGN133611100.00
CONT_ASSIGN133811100.00
CONT_ASSIGN134011100.00
CONT_ASSIGN134211100.00
CONT_ASSIGN134311100.00
CONT_ASSIGN134511100.00
CONT_ASSIGN134711100.00
CONT_ASSIGN134911100.00
CONT_ASSIGN135111100.00
ALWAYS135599100.00
ALWAYS13684141100.00
CONT_ASSIGN144400
CONT_ASSIGN145211100.00
CONT_ASSIGN145311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_prim_reg_top_1.0/rtl/otp_ctrl_prim_reg_top.sv' or '../src/lowrisc_ip_otp_ctrl_prim_reg_top_1.0/rtl/otp_ctrl_prim_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
77 1 1
89 1 1
90 1 1
118 1 1
119 1 1
1268 1 1
1269 1 1
1270 1 1
1271 1 1
1272 1 1
1273 1 1
1274 1 1
1275 1 1
1276 1 1
1279 1 1
1283 1 1
1295 1 1
1297 1 1
1299 1 1
1301 1 1
1303 1 1
1305 1 1
1306 1 1
1308 1 1
1310 1 1
1312 1 1
1314 1 1
1316 1 1
1317 1 1
1319 1 1
1320 1 1
1322 1 1
1324 1 1
1326 1 1
1327 1 1
1329 1 1
1331 1 1
1333 1 1
1335 1 1
1336 1 1
1338 1 1
1340 1 1
1342 1 1
1343 1 1
1345 1 1
1347 1 1
1349 1 1
1351 1 1
1355 1 1
1356 1 1
1357 1 1
1358 1 1
1359 1 1
1360 1 1
1361 1 1
1362 1 1
1363 1 1
1368 1 1
1369 1 1
1371 1 1
1372 1 1
1373 1 1
1374 1 1
1375 1 1
1379 1 1
1380 1 1
1381 1 1
1382 1 1
1383 1 1
1387 1 1
1391 1 1
1392 1 1
1393 1 1
1394 1 1
1395 1 1
1396 1 1
1397 1 1
1398 1 1
1399 1 1
1403 1 1
1404 1 1
1405 1 1
1406 1 1
1410 1 1
1411 1 1
1412 1 1
1413 1 1
1414 1 1
1415 1 1
1416 1 1
1420 1 1
1421 1 1
1422 1 1
1423 1 1
1427 1 1
1428 1 1
1429 1 1
1430 1 1
1444 unreachable
1452 1 1
1453 1 1


Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top
TotalCoveredPercent
Conditions9797100.00
Logical9797100.00
Non-Logical00
Event00

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT2,T4,T14

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T18,T19
10CoveredT256,T257,T258

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT17,T18,T19
010CoveredT256,T257,T258
100CoveredT17,T18,T19

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---
-1--2--3-StatusTestsExclude Annotation
000CoveredT1,T2,T3
001CoveredT256,T257,T258
010CoveredT2,T4,T11
100Excluded VC_COV_UNR

 LINE       1269
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR0_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT2,T4,T14
1CoveredT1,T2,T4

 LINE       1270
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR1_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT2,T4,T14

 LINE       1271
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR2_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT2,T4,T14

 LINE       1272
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR3_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT2,T4,T14

 LINE       1273
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR4_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT2,T4,T14

 LINE       1274
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR5_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT2,T4,T14

 LINE       1275
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR6_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT2,T4,T14

 LINE       1276
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR7_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT2,T4,T14

 LINE       1279
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T14

 LINE       1279
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T14
10CoveredT2,T4,T14

 LINE       1283
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[4] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T14,T12
11CoveredT2,T4,T11

 LINE       1283
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1111 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1111 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b0111 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b0011 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0011 & (~reg_be))))))
-1--2--3--4--5--6--7--8-StatusTests
00000000CoveredT2,T4,T14
00000001CoveredT2,T4,T12
00000010CoveredT2,T4,T12
00000100CoveredT2,T4,T12
00001000CoveredT2,T4,T12
00010000CoveredT2,T4,T12
00100000CoveredT2,T4,T12
01000000CoveredT2,T4,T12
10000000CoveredT1,T2,T3

 LINE       1283
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT2,T4,T12
10CoveredT2,T4,T14
11CoveredT1,T2,T3

 LINE       1283
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T4,T14
11CoveredT2,T4,T12

 LINE       1283
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T4,T14
11CoveredT2,T4,T12

 LINE       1283
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T4,T14
11CoveredT2,T4,T12

 LINE       1283
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T4,T14
11CoveredT2,T4,T12

 LINE       1283
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T4,T14
11CoveredT2,T4,T12

 LINE       1283
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T4,T14
11CoveredT2,T4,T12

 LINE       1283
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T4,T14
11CoveredT2,T4,T12

 LINE       1295
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT2,T14,T12
101CoveredT1,T2,T3
110CoveredT2,T4,T132
111CoveredT2,T14,T12

 LINE       1306
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT2,T14,T12
101CoveredT2,T4,T14
110CoveredT2,T4,T11
111CoveredT2,T14,T12

 LINE       1317
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT2,T14,T12
101CoveredT2,T4,T14
110CoveredT2,T4,T11
111CoveredT2,T14,T12

 LINE       1320
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT2,T14,T12
101CoveredT2,T4,T14
110CoveredT2,T4,T11
111CoveredT2,T14,T12

 LINE       1327
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT2,T14,T12
101CoveredT2,T4,T14
110CoveredT2,T4,T132
111CoveredT2,T14,T12

 LINE       1336
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT2,T14,T12
101CoveredT2,T4,T14
110CoveredT2,T4,T11
111CoveredT2,T14,T12

 LINE       1343
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT2,T14,T12
101CoveredT2,T4,T14
110CoveredT2,T4,T132
111CoveredT2,T14,T12

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 1279 2 2 100.00
IF 68 3 3 100.00
CASE 1369 9 9 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_prim_reg_top_1.0/rtl/otp_ctrl_prim_reg_top.sv' or '../src/lowrisc_ip_otp_ctrl_prim_reg_top_1.0/rtl/otp_ctrl_prim_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 1279 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T2,T4,T14
0 Covered T1,T2,T3


LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T17,T18,T19
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 1369 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T2,T3
addr_hit[1] Covered T2,T4,T14
addr_hit[2] Covered T2,T4,T14
addr_hit[3] Covered T2,T4,T14
addr_hit[4] Covered T2,T4,T14
addr_hit[5] Covered T2,T4,T14
addr_hit[6] Covered T2,T4,T14
addr_hit[7] Covered T2,T4,T14
default Covered T2,T4,T14


Assert Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
en2addrHit 439258479 92331 0 0
reAfterRv 439258479 92331 0 0
rePulse 439258479 27546 0 0
wePulse 439258479 64785 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 439258479 92331 0 0
T2 591032 2841 0 0
T3 10119 0 0 0
T4 208103 749 0 0
T5 40605 0 0 0
T6 58847 0 0 0
T7 9847 0 0 0
T8 48110 0 0 0
T9 13328 0 0 0
T10 20096 0 0 0
T11 0 76 0 0
T12 0 48 0 0
T14 215520 22 0 0
T31 0 80 0 0
T55 0 30 0 0
T90 0 206 0 0
T103 0 8 0 0
T223 0 40 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 439258479 92331 0 0
T2 591032 2841 0 0
T3 10119 0 0 0
T4 208103 749 0 0
T5 40605 0 0 0
T6 58847 0 0 0
T7 9847 0 0 0
T8 48110 0 0 0
T9 13328 0 0 0
T10 20096 0 0 0
T11 0 76 0 0
T12 0 48 0 0
T14 215520 22 0 0
T31 0 80 0 0
T55 0 30 0 0
T90 0 206 0 0
T103 0 8 0 0
T223 0 40 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 439258479 27546 0 0
T2 591032 169 0 0
T3 10119 0 0 0
T4 208103 39 0 0
T5 40605 0 0 0
T6 58847 0 0 0
T7 9847 0 0 0
T8 48110 0 0 0
T9 13328 0 0 0
T10 20096 0 0 0
T11 0 72 0 0
T12 0 24 0 0
T14 215520 11 0 0
T31 0 80 0 0
T55 0 15 0 0
T90 0 103 0 0
T103 0 4 0 0
T223 0 40 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 439258479 64785 0 0
T2 591032 2672 0 0
T3 10119 0 0 0
T4 208103 710 0 0
T5 40605 0 0 0
T6 58847 0 0 0
T7 9847 0 0 0
T8 48110 0 0 0
T9 13328 0 0 0
T10 20096 0 0 0
T11 0 4 0 0
T12 0 24 0 0
T14 215520 11 0 0
T55 0 15 0 0
T90 0 103 0 0
T93 0 104 0 0
T103 0 4 0 0
T132 0 179 0 0