Summary for Variable operation_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for operation_type
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
read_op |
27678 |
1 |
|
|
T2 |
69 |
|
T4 |
10 |
|
T5 |
18 |
write_op |
6491 |
1 |
|
|
T1 |
1 |
|
T2 |
23 |
|
T5 |
7 |
Summary for Variable read_access_locked
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for read_access_locked
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11336 |
1 |
|
|
T1 |
1 |
|
T2 |
31 |
|
T5 |
17 |
auto[1] |
22833 |
1 |
|
|
T2 |
61 |
|
T4 |
10 |
|
T5 |
8 |
Summary for Variable write_access_locked
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for write_access_locked
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
26202 |
1 |
|
|
T1 |
1 |
|
T2 |
92 |
|
T4 |
10 |
auto[1] |
7967 |
1 |
|
|
T9 |
51 |
|
T24 |
43 |
|
T6 |
92 |
Summary for Cross unbuf_part_access_cross
Samples crossed: read_access_locked write_access_locked operation_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for unbuf_part_access_cross
Bins
read_access_locked | write_access_locked | operation_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
read_op |
5383 |
1 |
|
|
T2 |
15 |
|
T5 |
13 |
|
T7 |
1 |
auto[0] |
auto[0] |
write_op |
2874 |
1 |
|
|
T1 |
1 |
|
T2 |
16 |
|
T5 |
4 |
auto[0] |
auto[1] |
read_op |
2301 |
1 |
|
|
T9 |
6 |
|
T24 |
9 |
|
T6 |
30 |
auto[0] |
auto[1] |
write_op |
778 |
1 |
|
|
T9 |
3 |
|
T24 |
2 |
|
T6 |
7 |
auto[1] |
auto[0] |
read_op |
15867 |
1 |
|
|
T2 |
54 |
|
T4 |
10 |
|
T5 |
5 |
auto[1] |
auto[0] |
write_op |
2078 |
1 |
|
|
T2 |
7 |
|
T5 |
3 |
|
T9 |
1 |
auto[1] |
auto[1] |
read_op |
4127 |
1 |
|
|
T9 |
35 |
|
T24 |
29 |
|
T6 |
47 |
auto[1] |
auto[1] |
write_op |
761 |
1 |
|
|
T9 |
7 |
|
T24 |
3 |
|
T6 |
8 |
Summary for Variable operation_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for operation_type
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
read_op |
28035 |
1 |
|
|
T1 |
2 |
|
T2 |
84 |
|
T3 |
12 |
write_op |
6390 |
1 |
|
|
T1 |
3 |
|
T2 |
18 |
|
T3 |
5 |
Summary for Variable read_access_locked
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for read_access_locked
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11354 |
1 |
|
|
T1 |
5 |
|
T2 |
28 |
|
T3 |
17 |
auto[1] |
23071 |
1 |
|
|
T2 |
74 |
|
T4 |
12 |
|
T5 |
3 |
Summary for Variable write_access_locked
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for write_access_locked
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
28878 |
1 |
|
|
T1 |
5 |
|
T2 |
102 |
|
T3 |
17 |
auto[1] |
5547 |
1 |
|
|
T9 |
42 |
|
T24 |
41 |
|
T6 |
57 |
Summary for Cross unbuf_part_access_cross
Samples crossed: read_access_locked write_access_locked operation_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for unbuf_part_access_cross
Bins
read_access_locked | write_access_locked | operation_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
read_op |
6089 |
1 |
|
|
T1 |
2 |
|
T2 |
19 |
|
T3 |
12 |
auto[0] |
auto[0] |
write_op |
3124 |
1 |
|
|
T1 |
3 |
|
T2 |
9 |
|
T3 |
5 |
auto[0] |
auto[1] |
read_op |
1593 |
1 |
|
|
T9 |
12 |
|
T24 |
5 |
|
T6 |
24 |
auto[0] |
auto[1] |
write_op |
548 |
1 |
|
|
T9 |
3 |
|
T24 |
4 |
|
T6 |
7 |
auto[1] |
auto[0] |
read_op |
17462 |
1 |
|
|
T2 |
65 |
|
T4 |
12 |
|
T5 |
2 |
auto[1] |
auto[0] |
write_op |
2203 |
1 |
|
|
T2 |
9 |
|
T5 |
1 |
|
T9 |
3 |
auto[1] |
auto[1] |
read_op |
2891 |
1 |
|
|
T9 |
21 |
|
T24 |
26 |
|
T6 |
23 |
auto[1] |
auto[1] |
write_op |
515 |
1 |
|
|
T9 |
6 |
|
T24 |
6 |
|
T6 |
3 |
Summary for Variable operation_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for operation_type
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
read_op |
28408 |
1 |
|
|
T2 |
58 |
|
T3 |
12 |
|
T4 |
31 |
write_op |
6999 |
1 |
|
|
T1 |
3 |
|
T2 |
16 |
|
T3 |
5 |
Summary for Variable read_access_locked
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for read_access_locked
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11835 |
1 |
|
|
T1 |
1 |
|
T2 |
11 |
|
T3 |
17 |
auto[1] |
23572 |
1 |
|
|
T1 |
2 |
|
T2 |
63 |
|
T4 |
30 |
Summary for Variable write_access_locked
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for write_access_locked
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
27002 |
1 |
|
|
T1 |
3 |
|
T2 |
74 |
|
T3 |
17 |
auto[1] |
8405 |
1 |
|
|
T9 |
36 |
|
T24 |
46 |
|
T6 |
76 |
Summary for Cross unbuf_part_access_cross
Samples crossed: read_access_locked write_access_locked operation_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for unbuf_part_access_cross
Bins
read_access_locked | write_access_locked | operation_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
read_op |
5535 |
1 |
|
|
T2 |
6 |
|
T3 |
12 |
|
T4 |
1 |
auto[0] |
auto[0] |
write_op |
3114 |
1 |
|
|
T1 |
1 |
|
T2 |
5 |
|
T3 |
5 |
auto[0] |
auto[1] |
read_op |
2336 |
1 |
|
|
T9 |
10 |
|
T24 |
10 |
|
T6 |
26 |
auto[0] |
auto[1] |
write_op |
850 |
1 |
|
|
T9 |
2 |
|
T24 |
3 |
|
T6 |
12 |
auto[1] |
auto[0] |
read_op |
16134 |
1 |
|
|
T2 |
52 |
|
T4 |
30 |
|
T5 |
2 |
auto[1] |
auto[0] |
write_op |
2219 |
1 |
|
|
T1 |
2 |
|
T2 |
11 |
|
T9 |
1 |
auto[1] |
auto[1] |
read_op |
4403 |
1 |
|
|
T9 |
19 |
|
T24 |
27 |
|
T6 |
32 |
auto[1] |
auto[1] |
write_op |
816 |
1 |
|
|
T9 |
5 |
|
T24 |
6 |
|
T6 |
6 |
Summary for Variable operation_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for operation_type
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
read_op |
26881 |
1 |
|
|
T1 |
8 |
|
T2 |
67 |
|
T3 |
18 |
write_op |
4782 |
1 |
|
|
T1 |
2 |
|
T2 |
10 |
|
T3 |
7 |
Summary for Variable read_access_locked
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for read_access_locked
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10390 |
1 |
|
|
T2 |
10 |
|
T3 |
25 |
|
T4 |
3 |
auto[1] |
21273 |
1 |
|
|
T1 |
10 |
|
T2 |
67 |
|
T4 |
26 |
Summary for Variable write_access_locked
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for write_access_locked
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
28703 |
1 |
|
|
T1 |
10 |
|
T2 |
77 |
|
T3 |
25 |
auto[1] |
2960 |
1 |
|
|
T6 |
15 |
|
T86 |
45 |
|
T94 |
63 |
Summary for Cross unbuf_part_access_cross
Samples crossed: read_access_locked write_access_locked operation_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for unbuf_part_access_cross
Bins
read_access_locked | write_access_locked | operation_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
read_op |
6598 |
1 |
|
|
T2 |
9 |
|
T3 |
18 |
|
T4 |
1 |
auto[0] |
auto[0] |
write_op |
2706 |
1 |
|
|
T2 |
1 |
|
T3 |
7 |
|
T4 |
2 |
auto[0] |
auto[1] |
read_op |
886 |
1 |
|
|
T6 |
8 |
|
T86 |
8 |
|
T94 |
28 |
auto[0] |
auto[1] |
write_op |
200 |
1 |
|
|
T6 |
2 |
|
T94 |
7 |
|
T74 |
2 |
auto[1] |
auto[0] |
read_op |
17743 |
1 |
|
|
T1 |
8 |
|
T2 |
58 |
|
T4 |
26 |
auto[1] |
auto[0] |
write_op |
1656 |
1 |
|
|
T1 |
2 |
|
T2 |
9 |
|
T9 |
4 |
auto[1] |
auto[1] |
read_op |
1654 |
1 |
|
|
T6 |
5 |
|
T86 |
34 |
|
T94 |
24 |
auto[1] |
auto[1] |
write_op |
220 |
1 |
|
|
T86 |
3 |
|
T94 |
4 |
|
T74 |
1 |
Summary for Variable operation_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for operation_type
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
read_op |
26814 |
1 |
|
|
T2 |
86 |
|
T3 |
6 |
|
T4 |
24 |
write_op |
6030 |
1 |
|
|
T1 |
1 |
|
T2 |
22 |
|
T3 |
3 |
Summary for Variable read_access_locked
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for read_access_locked
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10863 |
1 |
|
|
T1 |
1 |
|
T2 |
11 |
|
T3 |
9 |
auto[1] |
21981 |
1 |
|
|
T2 |
97 |
|
T4 |
24 |
|
T5 |
4 |
Summary for Variable write_access_locked
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for write_access_locked
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
24764 |
1 |
|
|
T1 |
1 |
|
T2 |
108 |
|
T3 |
9 |
auto[1] |
8080 |
1 |
|
|
T9 |
38 |
|
T24 |
38 |
|
T6 |
88 |
Summary for Cross unbuf_part_access_cross
Samples crossed: read_access_locked write_access_locked operation_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for unbuf_part_access_cross
Bins
read_access_locked | write_access_locked | operation_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
read_op |
4965 |
1 |
|
|
T2 |
5 |
|
T3 |
6 |
|
T5 |
15 |
auto[0] |
auto[0] |
write_op |
2750 |
1 |
|
|
T1 |
1 |
|
T2 |
6 |
|
T3 |
3 |
auto[0] |
auto[1] |
read_op |
2445 |
1 |
|
|
T9 |
6 |
|
T24 |
20 |
|
T6 |
29 |
auto[0] |
auto[1] |
write_op |
703 |
1 |
|
|
T9 |
2 |
|
T24 |
5 |
|
T6 |
8 |
auto[1] |
auto[0] |
read_op |
15185 |
1 |
|
|
T2 |
81 |
|
T4 |
24 |
|
T5 |
4 |
auto[1] |
auto[0] |
write_op |
1864 |
1 |
|
|
T2 |
16 |
|
T9 |
1 |
|
T24 |
2 |
auto[1] |
auto[1] |
read_op |
4219 |
1 |
|
|
T9 |
26 |
|
T24 |
9 |
|
T6 |
42 |
auto[1] |
auto[1] |
write_op |
713 |
1 |
|
|
T9 |
4 |
|
T24 |
4 |
|
T6 |
9 |