Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

24720603

1

T1

3801

T2

555087

T3

1276

full_word

8137507

1

T1

350

T2

157982

T3

225

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32857800	1			T1	4151		T2	713069		T3	1501
auto[TlIntgErrCmd]	112	1			T274	8		T275	8		T276	6
auto[TlIntgErrData]	100	1			T274	7		T275	10		T276	6
auto[TlIntgErrBoth]	98	1			T274	5		T275	2		T276	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9750493

1

T1

4034

T2

105585

T3

1242

auto[1]

23107617

1

T1

117

T2

607484

T3

259

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6168778	1			T1	3749		T2	63626		T3	1127
auto[TlIntgErrNone]	partial	auto[1]	18551547	1			T1	52		T2	491461		T3	149
auto[TlIntgErrNone]	full_word	auto[0]	3581572	1			T1	285		T2	41959		T3	115
auto[TlIntgErrNone]	full_word	auto[1]	4555903	1			T1	65		T2	116023		T3	110
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T274	1		T275	4		T276	4
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T274	7		T275	4		T276	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T366	1		T367	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T364	1		T368	1		-	-
auto[TlIntgErrData]	partial	auto[0]	43	1			T274	2		T275	4		T276	2
auto[TlIntgErrData]	partial	auto[1]	44	1			T274	4		T275	4		T276	3
auto[TlIntgErrData]	full_word	auto[0]	8	1			T275	2		T361	1		T369	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T274	1		T276	1		T282	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T274	1		T275	1		T276	4
auto[TlIntgErrBoth]	partial	auto[1]	48	1			T274	3		T275	1		T276	4
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T361	2		T370	1		T281	1
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T274	1		T361	1		T282	1