Line Coverage for Module :
prim_sync_reqack_data
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 0 | 0 | |
CONT_ASSIGN | 156 | 0 | 0 | |
ALWAYS | 159 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
93 |
1 |
1 |
153 |
|
unreachable |
156 |
|
unreachable |
159 |
|
unreachable |
160 |
|
unreachable |
162 |
|
unreachable |
Assert Coverage for Module :
prim_sync_reqack_data
Assertion Details
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460274078 |
553355 |
0 |
0 |
T1 |
34855 |
140 |
0 |
0 |
T2 |
935256 |
2348 |
0 |
0 |
T3 |
15086 |
0 |
0 |
0 |
T4 |
99939 |
450 |
0 |
0 |
T5 |
440148 |
474 |
0 |
0 |
T6 |
0 |
2528 |
0 |
0 |
T7 |
62862 |
644 |
0 |
0 |
T8 |
13768 |
0 |
0 |
0 |
T9 |
82484 |
834 |
0 |
0 |
T10 |
20012 |
0 |
0 |
0 |
T11 |
9427 |
0 |
0 |
0 |
T24 |
0 |
2083 |
0 |
0 |
T86 |
0 |
1490 |
0 |
0 |
T87 |
0 |
550 |
0 |
0 |
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460274078 |
553276 |
0 |
0 |
T1 |
34855 |
140 |
0 |
0 |
T2 |
935256 |
2348 |
0 |
0 |
T3 |
15086 |
0 |
0 |
0 |
T4 |
99939 |
450 |
0 |
0 |
T5 |
440148 |
474 |
0 |
0 |
T6 |
0 |
2528 |
0 |
0 |
T7 |
62862 |
644 |
0 |
0 |
T8 |
13768 |
0 |
0 |
0 |
T9 |
82484 |
834 |
0 |
0 |
T10 |
20012 |
0 |
0 |
0 |
T11 |
9427 |
0 |
0 |
0 |
T24 |
0 |
2083 |
0 |
0 |
T86 |
0 |
1490 |
0 |
0 |
T87 |
0 |
550 |
0 |
0 |