Group : push_pull_agent_pkg::req_ack_cg
dashboard | hierarchy | modlist | groups | tests | asserts


Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_edn_pull_agent[0].cov::m_req_ack_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_edn_pull_agent[0].cov::m_req_ack_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 3 0 3 100.00


Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_edn_pull_agent[0].cov::m_req_ack_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_ack 3 0 3 100.00 100 1 1 4



Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_flash_addr_pull_agent.cov::m_req_ack_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_flash_addr_pull_agent.cov::m_req_ack_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 3 0 3 100.00


Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_flash_addr_pull_agent.cov::m_req_ack_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_ack 3 0 3 100.00 100 1 1 4



Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_flash_data_pull_agent.cov::m_req_ack_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_flash_data_pull_agent.cov::m_req_ack_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 3 0 3 100.00


Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_flash_data_pull_agent.cov::m_req_ack_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_ack 3 0 3 100.00 100 1 1 4



Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_lc_prog_pull_agent.cov::m_req_ack_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_lc_prog_pull_agent.cov::m_req_ack_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 3 0 3 100.00


Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_lc_prog_pull_agent.cov::m_req_ack_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_ack 3 0 3 100.00 100 1 1 4



Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_otbn_pull_agent.cov::m_req_ack_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_otbn_pull_agent.cov::m_req_ack_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 3 0 3 100.00


Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_otbn_pull_agent.cov::m_req_ack_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_ack 3 0 3 100.00 100 1 1 4



Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[0].cov::m_req_ack_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[0].cov::m_req_ack_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 3 0 3 100.00


Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[0].cov::m_req_ack_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_ack 3 0 3 100.00 100 1 1 4



Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[1].cov::m_req_ack_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[1].cov::m_req_ack_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 3 0 3 100.00


Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[1].cov::m_req_ack_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_ack 3 0 3 100.00 100 1 1 4



Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[2].cov::m_req_ack_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[2].cov::m_req_ack_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 3 0 3 100.00


Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[2].cov::m_req_ack_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_ack 3 0 3 100.00 100 1 1 4



Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[3].cov::m_req_ack_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[3].cov::m_req_ack_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 3 0 3 100.00


Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[3].cov::m_req_ack_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_ack 3 0 3 100.00 100 1 1 4


Summary for Variable cp_req_ack

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 3 0 3 100.00


Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins
NAME   COUNT   STATUS   
ack_wo_req 0 Excluded
[auto[1]] 0 Excluded


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 536067 1 T2 4412 T3 276 T4 94
auto[2] 536464 1 T2 4412 T3 276 T4 94
auto[3] 536172 1 T2 4412 T3 276 T4 94


Summary for Variable cp_req_ack

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 3 0 3 100.00


Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins
NAME   COUNT   STATUS   
ack_wo_req 0 Excluded
[auto[1]] 0 Excluded


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6079 1 T2 47 T3 3 T4 1
auto[2] 6409 1 T2 47 T3 3 T4 1
auto[3] 6079 1 T2 47 T3 3 T4 1


Summary for Variable cp_req_ack

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 3 0 3 100.00


Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins
NAME   COUNT   STATUS   
ack_wo_req 0 Excluded
[auto[1]] 0 Excluded


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6061 1 T2 46 T3 3 T4 1
auto[2] 6637 1 T2 46 T3 3 T4 1
auto[3] 6062 1 T2 46 T3 3 T4 1


Summary for Variable cp_req_ack

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 3 0 3 100.00


Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins
NAME   COUNT   STATUS   
ack_wo_req 0 Excluded
[auto[1]] 0 Excluded


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 13428 1 T2 12 T3 5 T4 10
auto[2] 14238 1 T2 12 T3 5 T4 11
auto[3] 13467 1 T2 12 T3 5 T4 10


Summary for Variable cp_req_ack

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 3 0 3 100.00


Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins
NAME   COUNT   STATUS   
ack_wo_req 0 Excluded
[auto[1]] 0 Excluded


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6062 1 T2 52 T3 3 T4 1
auto[2] 6603 1 T2 53 T3 3 T4 1
auto[3] 6062 1 T2 52 T3 3 T4 1


Summary for Variable cp_req_ack

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 3 0 3 100.00


Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins
NAME   COUNT   STATUS   
ack_wo_req 0 Excluded
[auto[1]] 0 Excluded


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6050 1 T2 47 T3 3 T4 1
auto[2] 6881 1 T2 48 T3 3 T4 1
auto[3] 6050 1 T2 47 T3 3 T4 1


Summary for Variable cp_req_ack

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 3 0 3 100.00


Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins
NAME   COUNT   STATUS   
ack_wo_req 0 Excluded
[auto[1]] 0 Excluded


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6015 1 T2 47 T3 3 T4 1
auto[2] 6717 1 T2 48 T3 3 T4 1
auto[3] 6016 1 T2 47 T3 3 T4 1


Summary for Variable cp_req_ack

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 3 0 3 100.00


Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins
NAME   COUNT   STATUS   
ack_wo_req 0 Excluded
[auto[1]] 0 Excluded


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6004 1 T2 47 T3 3 T4 1
auto[2] 6770 1 T2 48 T3 3 T4 1
auto[3] 6004 1 T2 47 T3 3 T4 1


Summary for Variable cp_req_ack

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 3 0 3 100.00


Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins
NAME   COUNT   STATUS   
ack_wo_req 0 Excluded
[auto[1]] 0 Excluded


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 5935 1 T2 47 T3 3 T4 1
auto[2] 6598 1 T2 48 T3 3 T4 1
auto[3] 6033 1 T2 47 T3 3 T4 1