Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

25371420

1

T1

647

T2

153425

T3

4354

full_word

8424663

1

T1

280

T2

44645

T3

2244

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33795773	1			T1	927		T2	198070		T3	6598
auto[TlIntgErrCmd]	105	1			T230	12		T231	5		T232	5
auto[TlIntgErrData]	109	1			T230	5		T231	3		T232	3
auto[TlIntgErrBoth]	96	1			T230	3		T231	2		T232	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10122842

1

T1

605

T2

49312

T3

5947

auto[1]

23673241

1

T1

322

T2

148758

T3

651

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6394845	1			T1	473		T2	32314		T3	3960
auto[TlIntgErrNone]	partial	auto[1]	18976291	1			T1	174		T2	121111		T3	394
auto[TlIntgErrNone]	full_word	auto[0]	3727872	1			T1	132		T2	16998		T3	1987
auto[TlIntgErrNone]	full_word	auto[1]	4696765	1			T1	148		T2	27647		T3	257
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T230	4		T231	1		T232	2
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T230	8		T231	4		T232	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T238	1		T317	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T232	1		T315	1		T312	1
auto[TlIntgErrData]	partial	auto[0]	44	1			T230	2		T231	2		T232	1
auto[TlIntgErrData]	partial	auto[1]	55	1			T230	2		T231	1		T232	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T313	1		T314	1		T318	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T230	1		T238	2		T313	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T230	1		T315	3		T238	2
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T230	2		T231	2		T232	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T238	1		T311	1		T319	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T238	2		T318	1		T317	1