Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	497962693	8061067	0	0
check_regwen_rd_A	497962693	2663	0	0
check_timeout_rd_A	497962693	2199	0	0
check_trigger_regwen_rd_A	497962693	2708	0	0
consistency_check_period_rd_A	497962693	2913	0	0
creator_sw_cfg_read_lock_rd_A	497962693	2278	0	0
direct_access_address_rd_A	497962693	1868	0	0
direct_access_wdata_0_rd_A	497962693	1123	0	0
direct_access_wdata_1_rd_A	497962693	1319	0	0
integrity_check_period_rd_A	497962693	2628	0	0
intr_enable_rd_A	497962693	3350	0	0
owner_sw_cfg_read_lock_rd_A	497962693	2148	0	0
rot_creator_auth_codesign_read_lock_rd_A	497962693	2191	0	0
rot_creator_auth_state_read_lock_rd_A	497962693	1998	0	0
vendor_test_read_lock_rd_A	497962693	2052	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497962693	8061067	0	0
T2	349224	53933	0	0
T3	43967	0	0	0
T4	18253	0	0	0
T5	0	48742	0	0
T6	0	46679	0	0
T7	11714	0	0	0
T8	142819	0	0	0
T9	11071	0	0	0
T10	13879	0	0	0
T11	18308	0	0	0
T12	23361	0	0	0
T14	0	52669	0	0
T33	0	122313	0	0
T102	7394	0	0	0
T122	0	189305	0	0
T125	0	36414	0	0
T130	0	130804	0	0
T239	0	18857	0	0
T240	0	105293	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497962693	2663	0	0
T21	9963	0	0	0
T33	0	70	0	0
T41	10094	0	0	0
T69	45092	0	0	0
T97	576431	0	0	0
T98	26272	0	0	0
T122	0	119	0	0
T125	178863	33	0	0
T130	0	103	0	0
T184	13116	0	0	0
T199	13301	0	0	0
T210	14566	0	0	0
T214	12559	0	0	0
T242	0	120	0	0
T300	0	56	0	0
T301	0	100	0	0
T302	0	137	0	0
T303	0	135	0	0
T304	0	48	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497962693	2199	0	0
T21	9963	0	0	0
T33	0	121	0	0
T41	10094	0	0	0
T69	45092	0	0	0
T97	576431	0	0	0
T98	26272	0	0	0
T122	0	162	0	0
T125	178863	16	0	0
T130	0	77	0	0
T184	13116	0	0	0
T199	13301	0	0	0
T210	14566	0	0	0
T214	12559	0	0	0
T242	0	87	0	0
T300	0	92	0	0
T301	0	146	0	0
T302	0	138	0	0
T303	0	110	0	0
T304	0	68	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497962693	2708	0	0
T21	9963	0	0	0
T33	0	103	0	0
T41	10094	0	0	0
T69	45092	0	0	0
T97	576431	0	0	0
T98	26272	0	0	0
T122	0	98	0	0
T125	178863	11	0	0
T130	0	101	0	0
T184	13116	0	0	0
T199	13301	0	0	0
T210	14566	0	0	0
T214	12559	0	0	0
T242	0	72	0	0
T300	0	56	0	0
T301	0	84	0	0
T302	0	141	0	0
T303	0	95	0	0
T304	0	81	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497962693	2913	0	0
T21	9963	0	0	0
T33	0	88	0	0
T41	10094	0	0	0
T69	45092	0	0	0
T97	576431	0	0	0
T98	26272	0	0	0
T122	0	79	0	0
T125	178863	8	0	0
T130	0	79	0	0
T184	13116	0	0	0
T199	13301	0	0	0
T210	14566	0	0	0
T214	12559	0	0	0
T242	0	88	0	0
T300	0	68	0	0
T301	0	155	0	0
T302	0	158	0	0
T303	0	111	0	0
T304	0	111	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497962693	2278	0	0
T21	9963	0	0	0
T33	0	102	0	0
T41	10094	0	0	0
T69	45092	0	0	0
T97	576431	0	0	0
T98	26272	0	0	0
T122	0	78	0	0
T125	178863	60	0	0
T130	0	101	0	0
T184	13116	0	0	0
T199	13301	0	0	0
T210	14566	0	0	0
T214	12559	0	0	0
T242	0	86	0	0
T300	0	67	0	0
T301	0	210	0	0
T302	0	178	0	0
T303	0	84	0	0
T304	0	74	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497962693	1868	0	0
T21	9963	0	0	0
T33	0	82	0	0
T41	10094	0	0	0
T69	45092	0	0	0
T97	576431	0	0	0
T98	26272	0	0	0
T122	0	82	0	0
T125	178863	18	0	0
T130	0	71	0	0
T184	13116	0	0	0
T199	13301	0	0	0
T210	14566	0	0	0
T214	12559	0	0	0
T242	0	130	0	0
T300	0	82	0	0
T301	0	125	0	0
T302	0	231	0	0
T303	0	134	0	0
T304	0	67	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497962693	1123	0	0
T21	9963	0	0	0
T33	0	64	0	0
T41	10094	0	0	0
T69	45092	0	0	0
T97	576431	0	0	0
T98	26272	0	0	0
T122	0	77	0	0
T125	178863	32	0	0
T130	0	45	0	0
T184	13116	0	0	0
T199	13301	0	0	0
T210	14566	0	0	0
T214	12559	0	0	0
T242	0	52	0	0
T300	0	9	0	0
T301	0	134	0	0
T302	0	120	0	0
T303	0	40	0	0
T304	0	11	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497962693	1319	0	0
T21	9963	0	0	0
T33	0	36	0	0
T41	10094	0	0	0
T69	45092	0	0	0
T97	576431	0	0	0
T98	26272	0	0	0
T122	0	76	0	0
T125	178863	5	0	0
T130	0	79	0	0
T184	13116	0	0	0
T199	13301	0	0	0
T210	14566	0	0	0
T214	12559	0	0	0
T242	0	85	0	0
T300	0	35	0	0
T301	0	158	0	0
T302	0	109	0	0
T303	0	76	0	0
T304	0	53	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497962693	2628	0	0
T21	9963	0	0	0
T33	0	56	0	0
T41	10094	0	0	0
T69	45092	0	0	0
T97	576431	0	0	0
T98	26272	0	0	0
T122	0	81	0	0
T125	178863	22	0	0
T130	0	58	0	0
T184	13116	0	0	0
T199	13301	0	0	0
T210	14566	0	0	0
T214	12559	0	0	0
T242	0	61	0	0
T300	0	40	0	0
T301	0	86	0	0
T302	0	155	0	0
T303	0	78	0	0
T304	0	109	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497962693	3350	0	0
T21	9963	0	0	0
T33	0	48	0	0
T41	10094	0	0	0
T69	45092	0	0	0
T70	0	28	0	0
T97	576431	0	0	0
T98	26272	0	0	0
T122	0	106	0	0
T125	178863	15	0	0
T130	0	81	0	0
T179	0	9	0	0
T184	13116	0	0	0
T199	13301	0	0	0
T210	14566	0	0	0
T214	12559	0	0	0
T242	0	76	0	0
T300	0	75	0	0
T301	0	104	0	0
T302	0	123	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497962693	2148	0	0
T21	9963	0	0	0
T33	0	38	0	0
T41	10094	0	0	0
T69	45092	0	0	0
T97	576431	0	0	0
T98	26272	0	0	0
T122	0	117	0	0
T125	178863	24	0	0
T130	0	73	0	0
T184	13116	0	0	0
T199	13301	0	0	0
T210	14566	0	0	0
T214	12559	0	0	0
T242	0	91	0	0
T300	0	56	0	0
T301	0	124	0	0
T302	0	211	0	0
T303	0	132	0	0
T304	0	84	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497962693	2191	0	0
T21	9963	0	0	0
T33	0	100	0	0
T41	10094	0	0	0
T69	45092	0	0	0
T97	576431	0	0	0
T98	26272	0	0	0
T122	0	111	0	0
T125	178863	40	0	0
T130	0	63	0	0
T184	13116	0	0	0
T199	13301	0	0	0
T210	14566	0	0	0
T214	12559	0	0	0
T242	0	109	0	0
T300	0	64	0	0
T301	0	165	0	0
T302	0	169	0	0
T303	0	102	0	0
T304	0	98	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497962693	1998	0	0
T21	9963	0	0	0
T33	0	108	0	0
T41	10094	0	0	0
T69	45092	0	0	0
T97	576431	0	0	0
T98	26272	0	0	0
T122	0	95	0	0
T125	178863	18	0	0
T130	0	87	0	0
T184	13116	0	0	0
T199	13301	0	0	0
T210	14566	0	0	0
T214	12559	0	0	0
T242	0	83	0	0
T300	0	48	0	0
T301	0	177	0	0
T302	0	163	0	0
T303	0	122	0	0
T304	0	71	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497962693	2052	0	0
T21	9963	0	0	0
T33	0	80	0	0
T41	10094	0	0	0
T69	45092	0	0	0
T97	576431	0	0	0
T98	26272	0	0	0
T122	0	86	0	0
T125	178863	13	0	0
T130	0	97	0	0
T184	13116	0	0	0
T199	13301	0	0	0
T210	14566	0	0	0
T214	12559	0	0	0
T242	0	85	0	0
T300	0	69	0	0
T301	0	184	0	0
T302	0	100	0	0
T303	0	118	0	0
T304	0	66	0	0