Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.19	94.16	96.15	97.02		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.19	94.16	96.15	97.02		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T59,T69,T109

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T33,T40,T61

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T6,T7,T11
1	Covered	T26,T27,T28

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T74,T127,T128
1	Covered	T74,T127,T128

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T6,T7,T11
1	Covered	T7,T11,T12

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T11
1	1	Covered	T1,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T3,T5

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T6,T7,T11
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T3,T5
ReadWaitSt	252	Covered	T1,T3,T6
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T7,T11,T12
IdleSt->ReadSt	236	Covered	T1,T3,T5
InitSt->ErrorSt	315	Covered	T112,T134,T91
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T6,T14,T133
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T3,T5,T8
ReadSt->ReadWaitSt	252	Covered	T1,T3,T6
ReadWaitSt->ErrorSt	276	Covered	T129,T135,T136
ReadWaitSt->IdleSt	270	Covered	T1,T3,T6
ResetSt->ErrorSt	315	Covered	T74,T75,T76
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T3,T5,T8
CheckFailError	317	Covered	T74,T127,T128
FsmStateError	289	Covered	T7,T11,T12
MacroEccCorrError	221	Covered	T59,T69,T33
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T8,T9,T10
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T3,T5,T8
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T74,T127,T128
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T7,T11,T12
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T59,T69,T109
MacroEccCorrError->NoError	235	Covered	T33,T40,T61
NoError->AccessError	256	Covered	T3,T5,T8
NoError->CheckFailError	317	Covered	T74,T127,T128
NoError->FsmStateError	289	Covered	T7,T11,T12
NoError->MacroEccCorrError	221	Covered	T59,T69,T33

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T59,T69,T109
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T6,T14,T95
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T5
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T6
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T16,T67,T30
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T5,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T33,T40,T61
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T129,T135,T136
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T26,T27,T28
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T6,T7,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T11,T9,T37
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T11,T9,T37
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T6,T7,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T26,T27,T28

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T74,T127,T128
1	0	Covered	T74,T127,T128
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T7,T11,T12
1	0	Covered	T6,T7,T11
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	477016277	476139738	0	0
DigestKnown_A	477016277	476139738	0	0
DigestOffsetMustBeRepresentable_A	1146	1146	0	0
EccErrorState_A	477016277	19975	0	0
ErrorKnown_A	477016277	476139738	0	0
FsmStateKnown_A	477016277	476139738	0	0
InitDoneKnown_A	477016277	476139738	0	0
InitReadLocksPartition_A	477016277	100349482	0	0
InitWriteLocksPartition_A	477016277	100349482	0	0
OffsetMustBeBlockAligned_A	1146	1146	0	0
OtpAddrKnown_A	477016277	476139738	0	0
OtpCmdKnown_A	477016277	476139738	0	0
OtpErrorState_A	477016277	51	0	0
OtpReqKnown_A	477016277	476139738	0	0
OtpSizeKnown_A	477016277	476139738	0	0
OtpWdataKnown_A	477016277	476139738	0	0
ReadLockPropagation_A	477016277	188372442	0	0
SizeMustBeBlockAligned_A	1146	1146	0	0
TlulGntKnown_A	477016277	476139738	0	0
TlulRdataKnown_A	477016277	476139738	0	0
TlulReadOnReadLock_A	477016277	7849	0	0
TlulRerrorKnown_A	477016277	476139738	0	0
TlulRvalidKnown_A	477016277	476139738	0	0
WriteLockPropagation_A	477016277	2508588	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	477016277	29125514	0	0
u_state_regs_A	477016277	476139738	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	476139738	0	0
T1	37044	36759	0	0
T2	13289	12707	0	0
T3	62576	61082	0	0
T5	26529	25949	0	0
T6	15348	15085	0	0
T7	13155	12922	0	0
T11	12385	12138	0	0
T12	14945	14650	0	0
T13	9954	9694	0	0
T14	13064	12812	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	476139738	0	0
T1	37044	36759	0	0
T2	13289	12707	0	0
T3	62576	61082	0	0
T5	26529	25949	0	0
T6	15348	15085	0	0
T7	13155	12922	0	0
T11	12385	12138	0	0
T12	14945	14650	0	0
T13	9954	9694	0	0
T14	13064	12812	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1146	1146	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	19975	0	0
T33	41048	0	0	0
T74	8965	3120	0	0
T98	72990	0	0	0
T99	84913	0	0	0
T107	21245	0	0	0
T109	10639	0	0	0
T127	0	3207	0	0
T128	0	3568	0	0
T129	149654	0	0	0
T131	0	2302	0	0
T133	12338	0	0	0
T134	11200	0	0	0
T137	0	3914	0	0
T138	0	3864	0	0
T140	8847	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	476139738	0	0
T1	37044	36759	0	0
T2	13289	12707	0	0
T3	62576	61082	0	0
T5	26529	25949	0	0
T6	15348	15085	0	0
T7	13155	12922	0	0
T11	12385	12138	0	0
T12	14945	14650	0	0
T13	9954	9694	0	0
T14	13064	12812	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	476139738	0	0
T1	37044	36759	0	0
T2	13289	12707	0	0
T3	62576	61082	0	0
T5	26529	25949	0	0
T6	15348	15085	0	0
T7	13155	12922	0	0
T11	12385	12138	0	0
T12	14945	14650	0	0
T13	9954	9694	0	0
T14	13064	12812	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	476139738	0	0
T1	37044	36759	0	0
T2	13289	12707	0	0
T3	62576	61082	0	0
T5	26529	25949	0	0
T6	15348	15085	0	0
T7	13155	12922	0	0
T11	12385	12138	0	0
T12	14945	14650	0	0
T13	9954	9694	0	0
T14	13064	12812	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	100349482	0	0
T1	37044	322	0	0
T2	13289	700	0	0
T3	62576	1807	0	0
T5	26529	635	0	0
T6	15348	3860	0	0
T7	13155	4853	0	0
T11	12385	4257	0	0
T12	14945	4819	0	0
T13	9954	3234	0	0
T14	13064	3543	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	100349482	0	0
T1	37044	322	0	0
T2	13289	700	0	0
T3	62576	1807	0	0
T5	26529	635	0	0
T6	15348	3860	0	0
T7	13155	4853	0	0
T11	12385	4257	0	0
T12	14945	4819	0	0
T13	9954	3234	0	0
T14	13064	3543	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1146	1146	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	476139738	0	0
T1	37044	36759	0	0
T2	13289	12707	0	0
T3	62576	61082	0	0
T5	26529	25949	0	0
T6	15348	15085	0	0
T7	13155	12922	0	0
T11	12385	12138	0	0
T12	14945	14650	0	0
T13	9954	9694	0	0
T14	13064	12812	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	476139738	0	0
T1	37044	36759	0	0
T2	13289	12707	0	0
T3	62576	61082	0	0
T5	26529	25949	0	0
T6	15348	15085	0	0
T7	13155	12922	0	0
T11	12385	12138	0	0
T12	14945	14650	0	0
T13	9954	9694	0	0
T14	13064	12812	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	51	0	0
T6	15348	1	0	0
T7	13155	0	0	0
T8	240994	0	0	0
T11	12385	0	0	0
T12	14945	0	0	0
T13	9954	0	0	0
T14	13064	1	0	0
T36	40561	0	0	0
T95	0	1	0	0
T101	4051	0	0	0
T112	9988	0	0	0
T129	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	476139738	0	0
T1	37044	36759	0	0
T2	13289	12707	0	0
T3	62576	61082	0	0
T5	26529	25949	0	0
T6	15348	15085	0	0
T7	13155	12922	0	0
T11	12385	12138	0	0
T12	14945	14650	0	0
T13	9954	9694	0	0
T14	13064	12812	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	476139738	0	0
T1	37044	36759	0	0
T2	13289	12707	0	0
T3	62576	61082	0	0
T5	26529	25949	0	0
T6	15348	15085	0	0
T7	13155	12922	0	0
T11	12385	12138	0	0
T12	14945	14650	0	0
T13	9954	9694	0	0
T14	13064	12812	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	476139738	0	0
T1	37044	36759	0	0
T2	13289	12707	0	0
T3	62576	61082	0	0
T5	26529	25949	0	0
T6	15348	15085	0	0
T7	13155	12922	0	0
T11	12385	12138	0	0
T12	14945	14650	0	0
T13	9954	9694	0	0
T14	13064	12812	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	188372442	0	0
T1	37044	1397	0	0
T2	13289	5541	0	0
T3	62576	3327	0	0
T5	26529	3488	0	0
T6	15348	0	0	0
T7	13155	0	0	0
T8	0	181250	0	0
T9	0	193936	0	0
T10	0	194408	0	0
T11	12385	0	0	0
T12	14945	0	0	0
T13	9954	0	0	0
T14	13064	0	0	0
T15	0	25298	0	0
T20	0	26075	0	0
T105	0	2388	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1146	1146	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	476139738	0	0
T1	37044	36759	0	0
T2	13289	12707	0	0
T3	62576	61082	0	0
T5	26529	25949	0	0
T6	15348	15085	0	0
T7	13155	12922	0	0
T11	12385	12138	0	0
T12	14945	14650	0	0
T13	9954	9694	0	0
T14	13064	12812	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	476139738	0	0
T1	37044	36759	0	0
T2	13289	12707	0	0
T3	62576	61082	0	0
T5	26529	25949	0	0
T6	15348	15085	0	0
T7	13155	12922	0	0
T11	12385	12138	0	0
T12	14945	14650	0	0
T13	9954	9694	0	0
T14	13064	12812	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	7849	0	0
T3	62576	1	0	0
T5	26529	6	0	0
T6	15348	0	0	0
T7	13155	0	0	0
T8	240994	19	0	0
T9	0	17	0	0
T10	0	36	0	0
T11	12385	9	0	0
T12	14945	0	0	0
T13	9954	0	0	0
T14	13064	0	0	0
T15	0	5	0	0
T26	0	74	0	0
T37	0	1	0	0
T101	4051	0	0	0
T105	0	2	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	476139738	0	0
T1	37044	36759	0	0
T2	13289	12707	0	0
T3	62576	61082	0	0
T5	26529	25949	0	0
T6	15348	15085	0	0
T7	13155	12922	0	0
T11	12385	12138	0	0
T12	14945	14650	0	0
T13	9954	9694	0	0
T14	13064	12812	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	476139738	0	0
T1	37044	36759	0	0
T2	13289	12707	0	0
T3	62576	61082	0	0
T5	26529	25949	0	0
T6	15348	15085	0	0
T7	13155	12922	0	0
T11	12385	12138	0	0
T12	14945	14650	0	0
T13	9954	9694	0	0
T14	13064	12812	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	2508588	0	0
T3	62576	702	0	0
T5	26529	0	0	0
T6	15348	0	0	0
T7	13155	0	0	0
T8	240994	0	0	0
T11	12385	0	0	0
T12	14945	0	0	0
T13	9954	0	0	0
T14	13064	0	0	0
T16	0	109422	0	0
T32	0	12813	0	0
T40	0	4499	0	0
T67	0	56989	0	0
T96	0	3321	0	0
T97	0	1425	0	0
T98	0	2073	0	0
T99	0	2913	0	0
T100	0	3794	0	0
T101	4051	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	29125514	0	0
T1	37044	25315	0	0
T2	13289	0	0	0
T3	62576	50990	0	0
T5	26529	16579	0	0
T6	15348	2493	0	0
T7	13155	0	0	0
T11	12385	0	0	0
T12	14945	0	0	0
T13	9954	0	0	0
T14	13064	0	0	0
T20	0	57366	0	0
T32	0	347751	0	0
T37	0	17877	0	0
T96	0	24524	0	0
T97	0	54080	0	0
T98	0	50848	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	476139738	0	0
T1	37044	36759	0	0
T2	13289	12707	0	0
T3	62576	61082	0	0
T5	26529	25949	0	0
T6	15348	15085	0	0
T7	13155	12922	0	0
T11	12385	12138	0	0
T12	14945	14650	0	0
T13	9954	9694	0	0
T14	13064	12812	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T68,T59

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T37,T33,T129

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T6,T7,T11
1	Covered	T26,T27,T28

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T74,T75,T127
1	Covered	T74,T75,T127

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T6,T7,T11
1	Covered	T6,T7,T11

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T11
1	1	Covered	T1,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T3,T5

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T32

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T32

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T6,T7,T11
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T3,T5
ReadWaitSt	252	Covered	T1,T3,T6
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T7,T11,T12
IdleSt->ReadSt	236	Covered	T1,T3,T5
InitSt->ErrorSt	315	Covered	T112,T133,T134
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T6,T14,T109
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T3,T5,T8
ReadSt->ReadWaitSt	252	Covered	T1,T3,T6
ReadWaitSt->ErrorSt	276	Covered	T129,T136,T190
ReadWaitSt->IdleSt	270	Covered	T1,T3,T6
ResetSt->ErrorSt	315	Covered	T74,T75,T76
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T3,T5,T8
CheckFailError	317	Covered	T74,T75,T127
FsmStateError	289	Covered	T6,T7,T11
MacroEccCorrError	221	Covered	T13,T37,T68
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T8,T9,T10
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T3,T5,T8
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T74,T75,T127
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T6,T7,T11
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T13,T68,T59
MacroEccCorrError->NoError	235	Covered	T37,T33,T129
NoError->AccessError	256	Covered	T3,T5,T8
NoError->CheckFailError	317	Covered	T74,T75,T127
NoError->FsmStateError	289	Covered	T6,T7,T11
NoError->MacroEccCorrError	221	Covered	T13,T37,T68

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T13,T68,T59
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T109,T191,T192
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T5
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T6
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T9,T16,T173
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T5,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T37,T33,T129
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T129,T136,T190
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T26,T27,T28
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T6,T7,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T11,T9,T37
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T11,T9,T37
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T6,T7,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T26,T27,T28

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T74,T75,T127
1	0	Covered	T74,T75,T127
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T6,T7,T11
1	0	Covered	T6,T7,T11
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	477016277	476139738	0	0
DigestKnown_A	477016277	476139738	0	0
DigestOffsetMustBeRepresentable_A	1146	1146	0	0
EccErrorState_A	477016277	17516	0	0
ErrorKnown_A	477016277	476139738	0	0
FsmStateKnown_A	477016277	476139738	0	0
InitDoneKnown_A	477016277	476139738	0	0
InitReadLocksPartition_A	477016277	100532322	0	0
InitWriteLocksPartition_A	477016277	100532322	0	0
OffsetMustBeBlockAligned_A	1146	1146	0	0
OtpAddrKnown_A	477016277	476139738	0	0
OtpCmdKnown_A	477016277	476139738	0	0
OtpErrorState_A	477016277	39	0	0
OtpReqKnown_A	477016277	476139738	0	0
OtpSizeKnown_A	477016277	476139738	0	0
OtpWdataKnown_A	477016277	476139738	0	0
ReadLockPropagation_A	477016277	187511772	0	0
SizeMustBeBlockAligned_A	1146	1146	0	0
TlulGntKnown_A	477016277	476139738	0	0
TlulRdataKnown_A	477016277	476139738	0	0
TlulReadOnReadLock_A	477016277	7773	0	0
TlulRerrorKnown_A	477016277	476139738	0	0
TlulRvalidKnown_A	477016277	476139738	0	0
WriteLockPropagation_A	477016277	888058	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	477016277	11039463	0	0
u_state_regs_A	477016277	476139738	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	476139738	0	0
T1	37044	36759	0	0
T2	13289	12707	0	0
T3	62576	61082	0	0
T5	26529	25949	0	0
T6	15348	15085	0	0
T7	13155	12922	0	0
T11	12385	12138	0	0
T12	14945	14650	0	0
T13	9954	9694	0	0
T14	13064	12812	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	476139738	0	0
T1	37044	36759	0	0
T2	13289	12707	0	0
T3	62576	61082	0	0
T5	26529	25949	0	0
T6	15348	15085	0	0
T7	13155	12922	0	0
T11	12385	12138	0	0
T12	14945	14650	0	0
T13	9954	9694	0	0
T14	13064	12812	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1146	1146	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	17516	0	0
T33	41048	0	0	0
T74	8965	3120	0	0
T75	0	2718	0	0
T98	72990	0	0	0
T99	84913	0	0	0
T107	21245	0	0	0
T109	10639	0	0	0
T127	0	3207	0	0
T129	149654	0	0	0
T131	0	2302	0	0
T133	12338	0	0	0
T134	11200	0	0	0
T137	0	3914	0	0
T139	0	2255	0	0
T140	8847	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	476139738	0	0
T1	37044	36759	0	0
T2	13289	12707	0	0
T3	62576	61082	0	0
T5	26529	25949	0	0
T6	15348	15085	0	0
T7	13155	12922	0	0
T11	12385	12138	0	0
T12	14945	14650	0	0
T13	9954	9694	0	0
T14	13064	12812	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	476139738	0	0
T1	37044	36759	0	0
T2	13289	12707	0	0
T3	62576	61082	0	0
T5	26529	25949	0	0
T6	15348	15085	0	0
T7	13155	12922	0	0
T11	12385	12138	0	0
T12	14945	14650	0	0
T13	9954	9694	0	0
T14	13064	12812	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	476139738	0	0
T1	37044	36759	0	0
T2	13289	12707	0	0
T3	62576	61082	0	0
T5	26529	25949	0	0
T6	15348	15085	0	0
T7	13155	12922	0	0
T11	12385	12138	0	0
T12	14945	14650	0	0
T13	9954	9694	0	0
T14	13064	12812	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	100532322	0	0
T1	37044	373	0	0
T2	13289	751	0	0
T3	62576	2113	0	0
T5	26529	720	0	0
T6	15348	3894	0	0
T7	13155	4887	0	0
T11	12385	4325	0	0
T12	14945	4853	0	0
T13	9954	3285	0	0
T14	13064	3577	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	100532322	0	0
T1	37044	373	0	0
T2	13289	751	0	0
T3	62576	2113	0	0
T5	26529	720	0	0
T6	15348	3894	0	0
T7	13155	4887	0	0
T11	12385	4325	0	0
T12	14945	4853	0	0
T13	9954	3285	0	0
T14	13064	3577	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1146	1146	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	476139738	0	0
T1	37044	36759	0	0
T2	13289	12707	0	0
T3	62576	61082	0	0
T5	26529	25949	0	0
T6	15348	15085	0	0
T7	13155	12922	0	0
T11	12385	12138	0	0
T12	14945	14650	0	0
T13	9954	9694	0	0
T14	13064	12812	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	476139738	0	0
T1	37044	36759	0	0
T2	13289	12707	0	0
T3	62576	61082	0	0
T5	26529	25949	0	0
T6	15348	15085	0	0
T7	13155	12922	0	0
T11	12385	12138	0	0
T12	14945	14650	0	0
T13	9954	9694	0	0
T14	13064	12812	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	39	0	0
T40	45256	0	0	0
T75	15685	0	0	0
T83	10982	0	0	0
T90	25950	0	0	0
T100	72699	0	0	0
T109	10639	1	0	0
T129	149654	1	0	0
T136	0	1	0	0
T140	8847	0	0	0
T184	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0
T192	0	1	0	0
T193	0	1	0	0
T194	0	1	0	0
T195	0	1	0	0
T196	12030	0	0	0
T197	13445	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	476139738	0	0
T1	37044	36759	0	0
T2	13289	12707	0	0
T3	62576	61082	0	0
T5	26529	25949	0	0
T6	15348	15085	0	0
T7	13155	12922	0	0
T11	12385	12138	0	0
T12	14945	14650	0	0
T13	9954	9694	0	0
T14	13064	12812	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	476139738	0	0
T1	37044	36759	0	0
T2	13289	12707	0	0
T3	62576	61082	0	0
T5	26529	25949	0	0
T6	15348	15085	0	0
T7	13155	12922	0	0
T11	12385	12138	0	0
T12	14945	14650	0	0
T13	9954	9694	0	0
T14	13064	12812	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	476139738	0	0
T1	37044	36759	0	0
T2	13289	12707	0	0
T3	62576	61082	0	0
T5	26529	25949	0	0
T6	15348	15085	0	0
T7	13155	12922	0	0
T11	12385	12138	0	0
T12	14945	14650	0	0
T13	9954	9694	0	0
T14	13064	12812	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	187511772	0	0
T3	62576	2801	0	0
T5	26529	5450	0	0
T6	15348	0	0	0
T7	13155	0	0	0
T8	240994	181648	0	0
T9	0	192046	0	0
T10	0	194929	0	0
T11	12385	0	0	0
T12	14945	0	0	0
T13	9954	0	0	0
T14	13064	0	0	0
T15	0	23250	0	0
T20	0	28840	0	0
T32	0	21408	0	0
T37	0	2262	0	0
T96	0	8129	0	0
T101	4051	0	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1146	1146	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	476139738	0	0
T1	37044	36759	0	0
T2	13289	12707	0	0
T3	62576	61082	0	0
T5	26529	25949	0	0
T6	15348	15085	0	0
T7	13155	12922	0	0
T11	12385	12138	0	0
T12	14945	14650	0	0
T13	9954	9694	0	0
T14	13064	12812	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	476139738	0	0
T1	37044	36759	0	0
T2	13289	12707	0	0
T3	62576	61082	0	0
T5	26529	25949	0	0
T6	15348	15085	0	0
T7	13155	12922	0	0
T11	12385	12138	0	0
T12	14945	14650	0	0
T13	9954	9694	0	0
T14	13064	12812	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	7773	0	0
T3	62576	1	0	0
T5	26529	5	0	0
T6	15348	0	0	0
T7	13155	0	0	0
T8	240994	17	0	0
T9	0	16	0	0
T10	0	47	0	0
T11	12385	6	0	0
T12	14945	0	0	0
T13	9954	0	0	0
T14	13064	0	0	0
T20	0	6	0	0
T26	0	5	0	0
T37	0	1	0	0
T101	4051	0	0	0
T105	0	2	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	476139738	0	0
T1	37044	36759	0	0
T2	13289	12707	0	0
T3	62576	61082	0	0
T5	26529	25949	0	0
T6	15348	15085	0	0
T7	13155	12922	0	0
T11	12385	12138	0	0
T12	14945	14650	0	0
T13	9954	9694	0	0
T14	13064	12812	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	476139738	0	0
T1	37044	36759	0	0
T2	13289	12707	0	0
T3	62576	61082	0	0
T5	26529	25949	0	0
T6	15348	15085	0	0
T7	13155	12922	0	0
T11	12385	12138	0	0
T12	14945	14650	0	0
T13	9954	9694	0	0
T14	13064	12812	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	888058	0	0
T3	62576	1461	0	0
T5	26529	0	0	0
T6	15348	0	0	0
T7	13155	0	0	0
T8	240994	0	0	0
T11	12385	0	0	0
T12	14945	0	0	0
T13	9954	0	0	0
T14	13064	0	0	0
T16	0	20145	0	0
T40	0	9938	0	0
T101	4051	0	0	0
T102	0	6025	0	0
T164	0	9957	0	0
T173	0	5710	0	0
T198	0	10094	0	0
T199	0	29963	0	0
T200	0	13510	0	0
T201	0	377	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	11039463	0	0
T3	62576	40200	0	0
T5	26529	16528	0	0
T6	15348	0	0	0
T7	13155	0	0	0
T8	240994	0	0	0
T11	12385	0	0	0
T12	14945	0	0	0
T13	9954	0	0	0
T14	13064	0	0	0
T16	0	253428	0	0
T32	0	347513	0	0
T40	0	35579	0	0
T41	0	67925	0	0
T67	0	76105	0	0
T93	0	2411	0	0
T101	4051	0	0	0
T102	0	47249	0	0
T202	0	4790	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477016277	476139738	0	0
T1	37044	36759	0	0
T2	13289	12707	0	0
T3	62576	61082	0	0
T5	26529	25949	0	0
T6	15348	15085	0	0
T7	13155	12922	0	0
T11	12385	12138	0	0
T12	14945	14650	0	0
T13	9954	9694	0	0
T14	13064	12812	0	0