Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.14	94.16	96.15	96.75		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	450013315	7628195	0	0
check_regwen_rd_A	450013315	2426	0	0
check_timeout_rd_A	450013315	2296	0	0
check_trigger_regwen_rd_A	450013315	2604	0	0
consistency_check_period_rd_A	450013315	2881	0	0
creator_sw_cfg_read_lock_rd_A	450013315	2418	0	0
direct_access_address_rd_A	450013315	1930	0	0
direct_access_wdata_0_rd_A	450013315	1237	0	0
direct_access_wdata_1_rd_A	450013315	1471	0	0
integrity_check_period_rd_A	450013315	2610	0	0
intr_enable_rd_A	450013315	3471	0	0
owner_sw_cfg_read_lock_rd_A	450013315	2050	0	0
rot_creator_auth_codesign_read_lock_rd_A	450013315	2409	0	0
rot_creator_auth_state_read_lock_rd_A	450013315	2397	0	0
vendor_test_read_lock_rd_A	450013315	2189	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450013315	7628195	0	0
T4	377808	92940	0	0
T5	629555	0	0	0
T6	0	118025	0	0
T7	28888	0	0	0
T8	15528	0	0	0
T9	11546	0	0	0
T10	48958	0	0	0
T11	13177	0	0	0
T12	13171	0	0	0
T13	0	142841	0	0
T15	0	140996	0	0
T16	10139	0	0	0
T17	0	88438	0	0
T102	9790	0	0	0
T124	0	41805	0	0
T140	0	90351	0	0
T244	0	90748	0	0
T278	0	46795	0	0
T279	0	90758	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450013315	2426	0	0
T6	854207	137	0	0
T14	268930	0	0	0
T18	0	90	0	0
T20	0	229	0	0
T35	62401	0	0	0
T73	12884	0	0	0
T106	8574	0	0	0
T107	15121	0	0	0
T108	18219	0	0	0
T109	24221	0	0	0
T110	27798	0	0	0
T137	33061	0	0	0
T313	0	77	0	0
T314	0	63	0	0
T315	0	8	0	0
T316	0	66	0	0
T317	0	27	0	0
T318	0	125	0	0
T319	0	38	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450013315	2296	0	0
T6	854207	154	0	0
T14	268930	0	0	0
T18	0	149	0	0
T20	0	210	0	0
T35	62401	0	0	0
T73	12884	0	0	0
T106	8574	0	0	0
T107	15121	0	0	0
T108	18219	0	0	0
T109	24221	0	0	0
T110	27798	0	0	0
T137	33061	0	0	0
T313	0	74	0	0
T314	0	72	0	0
T315	0	32	0	0
T316	0	83	0	0
T317	0	19	0	0
T318	0	165	0	0
T319	0	119	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450013315	2604	0	0
T6	854207	130	0	0
T14	268930	0	0	0
T18	0	121	0	0
T20	0	222	0	0
T35	62401	0	0	0
T73	12884	0	0	0
T106	8574	0	0	0
T107	15121	0	0	0
T108	18219	0	0	0
T109	24221	0	0	0
T110	27798	0	0	0
T137	33061	0	0	0
T313	0	43	0	0
T314	0	94	0	0
T315	0	12	0	0
T316	0	43	0	0
T317	0	34	0	0
T318	0	162	0	0
T319	0	71	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450013315	2881	0	0
T6	854207	163	0	0
T14	268930	0	0	0
T18	0	132	0	0
T20	0	273	0	0
T35	62401	0	0	0
T73	12884	0	0	0
T106	8574	0	0	0
T107	15121	0	0	0
T108	18219	0	0	0
T109	24221	0	0	0
T110	27798	0	0	0
T137	33061	0	0	0
T313	0	98	0	0
T314	0	88	0	0
T315	0	24	0	0
T316	0	60	0	0
T317	0	35	0	0
T318	0	109	0	0
T319	0	76	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450013315	2418	0	0
T6	854207	193	0	0
T14	268930	0	0	0
T18	0	119	0	0
T20	0	247	0	0
T35	62401	0	0	0
T73	12884	0	0	0
T106	8574	0	0	0
T107	15121	0	0	0
T108	18219	0	0	0
T109	24221	0	0	0
T110	27798	0	0	0
T137	33061	0	0	0
T313	0	67	0	0
T314	0	104	0	0
T315	0	66	0	0
T316	0	48	0	0
T317	0	48	0	0
T318	0	200	0	0
T319	0	61	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450013315	1930	0	0
T6	854207	121	0	0
T14	268930	0	0	0
T18	0	153	0	0
T20	0	233	0	0
T35	62401	0	0	0
T73	12884	0	0	0
T106	8574	0	0	0
T107	15121	0	0	0
T108	18219	0	0	0
T109	24221	0	0	0
T110	27798	0	0	0
T137	33061	0	0	0
T313	0	89	0	0
T314	0	103	0	0
T315	0	53	0	0
T316	0	28	0	0
T317	0	46	0	0
T318	0	159	0	0
T319	0	66	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450013315	1237	0	0
T6	854207	79	0	0
T14	268930	0	0	0
T18	0	103	0	0
T20	0	168	0	0
T35	62401	0	0	0
T73	12884	0	0	0
T106	8574	0	0	0
T107	15121	0	0	0
T108	18219	0	0	0
T109	24221	0	0	0
T110	27798	0	0	0
T137	33061	0	0	0
T313	0	70	0	0
T314	0	49	0	0
T315	0	35	0	0
T316	0	35	0	0
T317	0	1	0	0
T318	0	127	0	0
T319	0	25	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450013315	1471	0	0
T6	854207	110	0	0
T14	268930	0	0	0
T18	0	85	0	0
T20	0	194	0	0
T35	62401	0	0	0
T73	12884	0	0	0
T106	8574	0	0	0
T107	15121	0	0	0
T108	18219	0	0	0
T109	24221	0	0	0
T110	27798	0	0	0
T137	33061	0	0	0
T313	0	46	0	0
T314	0	93	0	0
T315	0	19	0	0
T316	0	33	0	0
T317	0	7	0	0
T318	0	148	0	0
T319	0	99	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450013315	2610	0	0
T6	854207	121	0	0
T14	268930	0	0	0
T18	0	153	0	0
T20	0	206	0	0
T35	62401	0	0	0
T73	12884	0	0	0
T106	8574	0	0	0
T107	15121	0	0	0
T108	18219	0	0	0
T109	24221	0	0	0
T110	27798	0	0	0
T137	33061	0	0	0
T313	0	101	0	0
T314	0	80	0	0
T315	0	35	0	0
T316	0	43	0	0
T317	0	35	0	0
T318	0	185	0	0
T319	0	59	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450013315	3471	0	0
T6	854207	178	0	0
T14	268930	0	0	0
T18	0	172	0	0
T20	0	235	0	0
T35	62401	0	0	0
T73	12884	0	0	0
T88	0	32	0	0
T106	8574	0	0	0
T107	15121	0	0	0
T108	18219	0	0	0
T109	24221	0	0	0
T110	27798	0	0	0
T137	33061	0	0	0
T313	0	36	0	0
T314	0	113	0	0
T315	0	72	0	0
T316	0	64	0	0
T317	0	46	0	0
T320	0	6	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450013315	2050	0	0
T6	854207	157	0	0
T14	268930	0	0	0
T18	0	143	0	0
T20	0	161	0	0
T35	62401	0	0	0
T73	12884	0	0	0
T106	8574	0	0	0
T107	15121	0	0	0
T108	18219	0	0	0
T109	24221	0	0	0
T110	27798	0	0	0
T137	33061	0	0	0
T313	0	36	0	0
T314	0	75	0	0
T315	0	31	0	0
T316	0	41	0	0
T317	0	42	0	0
T318	0	134	0	0
T319	0	68	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450013315	2409	0	0
T6	854207	123	0	0
T14	268930	0	0	0
T18	0	125	0	0
T20	0	248	0	0
T35	62401	0	0	0
T73	12884	0	0	0
T106	8574	0	0	0
T107	15121	0	0	0
T108	18219	0	0	0
T109	24221	0	0	0
T110	27798	0	0	0
T137	33061	0	0	0
T313	0	79	0	0
T314	0	81	0	0
T315	0	28	0	0
T316	0	46	0	0
T317	0	31	0	0
T318	0	163	0	0
T319	0	76	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450013315	2397	0	0
T6	854207	199	0	0
T14	268930	0	0	0
T18	0	108	0	0
T20	0	232	0	0
T35	62401	0	0	0
T73	12884	0	0	0
T106	8574	0	0	0
T107	15121	0	0	0
T108	18219	0	0	0
T109	24221	0	0	0
T110	27798	0	0	0
T137	33061	0	0	0
T313	0	79	0	0
T314	0	74	0	0
T315	0	22	0	0
T316	0	37	0	0
T317	0	34	0	0
T318	0	159	0	0
T319	0	50	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450013315	2189	0	0
T6	854207	195	0	0
T14	268930	0	0	0
T18	0	75	0	0
T20	0	166	0	0
T35	62401	0	0	0
T73	12884	0	0	0
T106	8574	0	0	0
T107	15121	0	0	0
T108	18219	0	0	0
T109	24221	0	0	0
T110	27798	0	0	0
T137	33061	0	0	0
T313	0	84	0	0
T314	0	81	0	0
T315	0	29	0	0
T316	0	90	0	0
T317	0	53	0	0
T318	0	207	0	0
T319	0	83	0	0