Group : otp_ctrl_env_pkg::otp_ctrl_unbuf_access_lock_cg_wrap::unbuf_access_lock_cg
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Group : otp_ctrl_env_pkg::otp_ctrl_unbuf_access_lock_cg_wrap::unbuf_access_lock_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

5 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
buf_err_code_cg_wrap[CreatorSwCfgIdx] 100.00 1 100 1 64 64
buf_err_code_cg_wrap[OwnerSwCfgIdx] 100.00 1 100 1 64 64
buf_err_code_cg_wrap[RotCreatorAuthCodesignIdx] 100.00 1 100 1 64 64
buf_err_code_cg_wrap[RotCreatorAuthStateIdx] 100.00 1 100 1 64 64
buf_err_code_cg_wrap[VendorTestIdx] 100.00 1 100 1 64 64




Group Instance : buf_err_code_cg_wrap[CreatorSwCfgIdx]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance buf_err_code_cg_wrap[CreatorSwCfgIdx]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group Instance buf_err_code_cg_wrap[CreatorSwCfgIdx]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
operation_type 2 0 2 100.00 100 1 1 0
read_access_locked 2 0 2 100.00 100 1 1 2
write_access_locked 2 0 2 100.00 100 1 1 2


Crosses for Group Instance buf_err_code_cg_wrap[CreatorSwCfgIdx]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
unbuf_part_access_cross 8 0 8 100.00 100 1 1 0



Group Instance : buf_err_code_cg_wrap[OwnerSwCfgIdx]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance buf_err_code_cg_wrap[OwnerSwCfgIdx]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group Instance buf_err_code_cg_wrap[OwnerSwCfgIdx]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
operation_type 2 0 2 100.00 100 1 1 0
read_access_locked 2 0 2 100.00 100 1 1 2
write_access_locked 2 0 2 100.00 100 1 1 2


Crosses for Group Instance buf_err_code_cg_wrap[OwnerSwCfgIdx]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
unbuf_part_access_cross 8 0 8 100.00 100 1 1 0



Group Instance : buf_err_code_cg_wrap[RotCreatorAuthCodesignIdx]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance buf_err_code_cg_wrap[RotCreatorAuthCodesignIdx]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group Instance buf_err_code_cg_wrap[RotCreatorAuthCodesignIdx]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
operation_type 2 0 2 100.00 100 1 1 0
read_access_locked 2 0 2 100.00 100 1 1 2
write_access_locked 2 0 2 100.00 100 1 1 2


Crosses for Group Instance buf_err_code_cg_wrap[RotCreatorAuthCodesignIdx]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
unbuf_part_access_cross 8 0 8 100.00 100 1 1 0



Group Instance : buf_err_code_cg_wrap[RotCreatorAuthStateIdx]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance buf_err_code_cg_wrap[RotCreatorAuthStateIdx]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group Instance buf_err_code_cg_wrap[RotCreatorAuthStateIdx]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
operation_type 2 0 2 100.00 100 1 1 0
read_access_locked 2 0 2 100.00 100 1 1 2
write_access_locked 2 0 2 100.00 100 1 1 2


Crosses for Group Instance buf_err_code_cg_wrap[RotCreatorAuthStateIdx]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
unbuf_part_access_cross 8 0 8 100.00 100 1 1 0



Group Instance : buf_err_code_cg_wrap[VendorTestIdx]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance buf_err_code_cg_wrap[VendorTestIdx]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group Instance buf_err_code_cg_wrap[VendorTestIdx]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
operation_type 2 0 2 100.00 100 1 1 0
read_access_locked 2 0 2 100.00 100 1 1 2
write_access_locked 2 0 2 100.00 100 1 1 2


Crosses for Group Instance buf_err_code_cg_wrap[VendorTestIdx]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
unbuf_part_access_cross 8 0 8 100.00 100 1 1 0


Summary for Variable operation_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for operation_type

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
read_op 28036 1 T1 8 T2 12 T3 4
write_op 6599 1 T1 3 T2 6 T3 2



Summary for Variable read_access_locked

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for read_access_locked

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11551 1 T1 11 T2 18 T3 5
auto[1] 23084 1 T3 1 T6 20 T10 11



Summary for Variable write_access_locked

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for write_access_locked

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 25943 1 T1 11 T2 18 T3 6
auto[1] 8692 1 T18 2 T57 4 T30 148



Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for unbuf_part_access_cross

Bins
read_access_lockedwrite_access_lockedoperation_typeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] read_op 5246 1 T1 8 T2 12 T3 3
auto[0] auto[0] write_op 2934 1 T1 3 T2 6 T3 2
auto[0] auto[1] read_op 2591 1 T18 1 T57 2 T30 47
auto[0] auto[1] write_op 780 1 T18 1 T57 2 T30 12
auto[1] auto[0] read_op 15698 1 T3 1 T6 20 T10 11
auto[1] auto[0] write_op 2065 1 T7 22 T40 2 T8 11
auto[1] auto[1] read_op 4501 1 T30 83 T32 24 T83 2
auto[1] auto[1] write_op 820 1 T30 6 T31 2 T32 3


Summary for Variable operation_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for operation_type

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
read_op 28979 1 T1 2 T2 6 T3 6
write_op 6564 1 T1 1 T2 3 T3 1



Summary for Variable read_access_locked

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for read_access_locked

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11746 1 T1 3 T2 9 T3 4
auto[1] 23797 1 T3 3 T6 20 T10 3



Summary for Variable write_access_locked

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for write_access_locked

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 29074 1 T1 3 T2 9 T3 7
auto[1] 6469 1 T30 139 T31 28 T32 27



Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for unbuf_part_access_cross

Bins
read_access_lockedwrite_access_lockedoperation_typeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] read_op 6143 1 T1 2 T2 6 T3 3
auto[0] auto[0] write_op 3206 1 T1 1 T2 3 T3 1
auto[0] auto[1] read_op 1794 1 T30 25 T31 11 T32 2
auto[0] auto[1] write_op 603 1 T30 8 T31 4 T32 3
auto[1] auto[0] read_op 17608 1 T3 3 T6 20 T10 2
auto[1] auto[0] write_op 2117 1 T10 1 T7 24 T53 3
auto[1] auto[1] read_op 3434 1 T30 90 T31 10 T32 20
auto[1] auto[1] write_op 638 1 T30 16 T31 3 T32 2


Summary for Variable operation_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for operation_type

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
read_op 29041 1 T1 8 T2 4 T3 9
write_op 6991 1 T1 4 T2 2 T3 4



Summary for Variable read_access_locked

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for read_access_locked

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11963 1 T1 12 T2 6 T3 4
auto[1] 24069 1 T3 9 T6 20 T10 16



Summary for Variable write_access_locked

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for write_access_locked

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 26926 1 T1 12 T2 6 T3 10
auto[1] 9106 1 T3 3 T57 9 T30 153



Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for unbuf_part_access_cross

Bins
read_access_lockedwrite_access_lockedoperation_typeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] read_op 5462 1 T1 8 T2 4 T3 1
auto[0] auto[0] write_op 3074 1 T1 4 T2 2 T3 2
auto[0] auto[1] read_op 2549 1 T3 1 T57 6 T30 38
auto[0] auto[1] write_op 878 1 T57 3 T30 19 T31 1
auto[1] auto[0] read_op 16266 1 T3 5 T6 20 T10 13
auto[1] auto[0] write_op 2124 1 T3 2 T10 3 T7 37
auto[1] auto[1] read_op 4764 1 T3 2 T30 85 T31 3
auto[1] auto[1] write_op 915 1 T30 11 T31 2 T47 3


Summary for Variable operation_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for operation_type

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
read_op 27602 1 T1 6 T2 10 T3 10
write_op 4819 1 T1 3 T2 4 T3 4



Summary for Variable read_access_locked

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for read_access_locked

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 10691 1 T1 9 T2 14 T6 3
auto[1] 21730 1 T3 14 T6 14 T10 12



Summary for Variable write_access_locked

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for write_access_locked

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 29496 1 T1 9 T2 14 T3 11
auto[1] 2925 1 T3 3 T57 4 T30 34



Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for unbuf_part_access_cross

Bins
read_access_lockedwrite_access_lockedoperation_typeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] read_op 6778 1 T1 6 T2 10 T6 2
auto[0] auto[0] write_op 2734 1 T1 3 T2 4 T6 1
auto[0] auto[1] read_op 955 1 T57 3 T30 10 T47 9
auto[0] auto[1] write_op 224 1 T57 1 T47 2 T110 5
auto[1] auto[0] read_op 18315 1 T3 8 T6 14 T10 11
auto[1] auto[0] write_op 1669 1 T3 3 T10 1 T122 1
auto[1] auto[1] read_op 1554 1 T3 2 T30 22 T47 27
auto[1] auto[1] write_op 192 1 T3 1 T30 2 T47 2


Summary for Variable operation_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for operation_type

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
read_op 28166 1 T1 2 T2 4 T3 5
write_op 6103 1 T1 1 T2 2 T3 4



Summary for Variable read_access_locked

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for read_access_locked

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11363 1 T1 3 T2 6 T3 2
auto[1] 22906 1 T3 7 T6 18 T10 11



Summary for Variable write_access_locked

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for write_access_locked

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 25610 1 T1 3 T2 6 T3 7
auto[1] 8659 1 T3 2 T18 1 T57 16



Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for unbuf_part_access_cross

Bins
read_access_lockedwrite_access_lockedoperation_typeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] read_op 5323 1 T1 2 T2 4 T6 2
auto[0] auto[0] write_op 2828 1 T1 1 T2 2 T6 2
auto[0] auto[1] read_op 2494 1 T3 1 T57 10 T30 57
auto[0] auto[1] write_op 718 1 T3 1 T18 1 T57 1
auto[1] auto[0] read_op 15622 1 T3 4 T6 18 T10 9
auto[1] auto[0] write_op 1837 1 T3 3 T10 2 T122 1
auto[1] auto[1] read_op 4727 1 T57 5 T30 130 T32 26
auto[1] auto[1] write_op 720 1 T30 13 T32 3 T83 2

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