Unified Coverage Report :: Module :: prim_lfsr

Module : prim_lfsr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.72			80.72

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lfsr_0.1/rtl/prim_lfsr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[0].u_prim_lfsr	80.72			80.72
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[1].u_prim_lfsr	80.72			80.72

---

Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[0].u_prim_lfsr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.72			80.72

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.72			80.72

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_prim_double_lfsr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[1].u_prim_lfsr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.72			80.72

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.72			80.72

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_prim_double_lfsr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_lfsr

	Total	Covered	Percent
Totals	5	4	80.00
Total Bits	166	134	80.72
Total Bits 0->1	83	67	80.72
Total Bits 1->0	83	67	80.72

Ports	5	4	80.00
Port Bits	166	134	80.72
Port Bits 0->1	83	67	80.72
Port Bits 1->0	83	67	80.72

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
seed_en_i	Unreachable	Unreachable		Unreachable		INPUT
seed_i[39:0]	Unreachable	Unreachable		Unreachable		INPUT
lfsr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
entropy_i[1:0]	Yes	Yes	T16	Yes	T16	INPUT
entropy_i[4:2]	No	No		No		INPUT
entropy_i[7:5]	Yes	Yes	T16	Yes	T16	INPUT
entropy_i[8]	No	No		No		INPUT
entropy_i[10:9]	Yes	Yes	T16	Yes	T16	INPUT
entropy_i[13:11]	No	No		No		INPUT
entropy_i[19:14]	Yes	Yes	T16	Yes	T16	INPUT
entropy_i[22:20]	No	No		No		INPUT
entropy_i[25:23]	Yes	Yes	T16	Yes	T16	INPUT
entropy_i[28:26]	No	No		No		INPUT
entropy_i[30:29]	Yes	Yes	T16	Yes	T16	INPUT
entropy_i[31]	No	No		No		INPUT
entropy_i[33:32]	Yes	Yes	T16	Yes	T16	INPUT
entropy_i[35:34]	No	No		No		INPUT
entropy_i[39:36]	Yes	Yes	T16	Yes	T16	INPUT
state_o[39:0]	Yes	Yes	T2,T3,T6	Yes	T2,T3,T6	OUTPUT

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[0].u_prim_lfsr

	Total	Covered	Percent
Totals	5	4	80.00
Total Bits	166	134	80.72
Total Bits 0->1	83	67	80.72
Total Bits 1->0	83	67	80.72

Ports	5	4	80.00
Port Bits	166	134	80.72
Port Bits 0->1	83	67	80.72
Port Bits 1->0	83	67	80.72

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
seed_en_i	Unreachable	Unreachable		Unreachable		INPUT
seed_i[39:0]	Unreachable	Unreachable		Unreachable		INPUT
lfsr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
entropy_i[1:0]	Yes	Yes	T16	Yes	T16	INPUT
entropy_i[4:2]	No	No		No		INPUT
entropy_i[7:5]	Yes	Yes	T16	Yes	T16	INPUT
entropy_i[8]	No	No		No		INPUT
entropy_i[10:9]	Yes	Yes	T16	Yes	T16	INPUT
entropy_i[13:11]	No	No		No		INPUT
entropy_i[19:14]	Yes	Yes	T16	Yes	T16	INPUT
entropy_i[22:20]	No	No		No		INPUT
entropy_i[25:23]	Yes	Yes	T16	Yes	T16	INPUT
entropy_i[28:26]	No	No		No		INPUT
entropy_i[30:29]	Yes	Yes	T16	Yes	T16	INPUT
entropy_i[31]	No	No		No		INPUT
entropy_i[33:32]	Yes	Yes	T16	Yes	T16	INPUT
entropy_i[35:34]	No	No		No		INPUT
entropy_i[39:36]	Yes	Yes	T16	Yes	T16	INPUT
state_o[39:0]	Yes	Yes	T2,T3,T6	Yes	T2,T3,T6	OUTPUT

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[1].u_prim_lfsr

	Total	Covered	Percent
Totals	5	4	80.00
Total Bits	166	134	80.72
Total Bits 0->1	83	67	80.72
Total Bits 1->0	83	67	80.72

Ports	5	4	80.00
Port Bits	166	134	80.72
Port Bits 0->1	83	67	80.72
Port Bits 1->0	83	67	80.72

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
seed_en_i	Unreachable	Unreachable		Unreachable		INPUT
seed_i[39:0]	Unreachable	Unreachable		Unreachable		INPUT
lfsr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
entropy_i[1:0]	Yes	Yes	T16	Yes	T16	INPUT
entropy_i[4:2]	No	No		No		INPUT
entropy_i[7:5]	Yes	Yes	T16	Yes	T16	INPUT
entropy_i[8]	No	No		No		INPUT
entropy_i[10:9]	Yes	Yes	T16	Yes	T16	INPUT
entropy_i[13:11]	No	No		No		INPUT
entropy_i[19:14]	Yes	Yes	T16	Yes	T16	INPUT
entropy_i[22:20]	No	No		No		INPUT
entropy_i[25:23]	Yes	Yes	T16	Yes	T16	INPUT
entropy_i[28:26]	No	No		No		INPUT
entropy_i[30:29]	Yes	Yes	T16	Yes	T16	INPUT
entropy_i[31]	No	No		No		INPUT
entropy_i[33:32]	Yes	Yes	T16	Yes	T16	INPUT
entropy_i[35:34]	No	No		No		INPUT
entropy_i[39:36]	Yes	Yes	T16	Yes	T16	INPUT
state_o[39:0]	Yes	Yes	T2,T3,T6	Yes	T2,T3,T6	OUTPUT