Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	94.16	96.15	96.83		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	480779676	8130389	0	0
check_regwen_rd_A	480779676	3433	0	0
check_timeout_rd_A	480779676	2630	0	0
check_trigger_regwen_rd_A	480779676	3486	0	0
consistency_check_period_rd_A	480779676	3585	0	0
creator_sw_cfg_read_lock_rd_A	480779676	2372	0	0
direct_access_address_rd_A	480779676	2223	0	0
direct_access_wdata_0_rd_A	480779676	1240	0	0
direct_access_wdata_1_rd_A	480779676	1558	0	0
integrity_check_period_rd_A	480779676	3538	0	0
intr_enable_rd_A	480779676	4490	0	0
owner_sw_cfg_read_lock_rd_A	480779676	2289	0	0
rot_creator_auth_codesign_read_lock_rd_A	480779676	2605	0	0
rot_creator_auth_state_read_lock_rd_A	480779676	2319	0	0
vendor_test_read_lock_rd_A	480779676	2309	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480779676	8130389	0	0
T7	948204	171185	0	0
T8	0	58316	0	0
T14	0	137787	0	0
T17	5811	0	0	0
T18	22811	0	0	0
T19	0	76038	0	0
T20	0	82841	0	0
T24	931853	0	0	0
T40	38472	0	0	0
T44	0	104201	0	0
T45	0	64540	0	0
T46	0	40786	0	0
T51	15758	0	0	0
T53	66825	0	0	0
T62	12065	0	0	0
T120	16341	0	0	0
T123	11802	0	0	0
T151	0	34199	0	0
T243	0	103831	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480779676	3433	0	0
T14	736216	65	0	0
T19	0	53	0	0
T22	0	79	0	0
T30	531275	0	0	0
T31	72855	0	0	0
T57	136352	0	0	0
T65	13528	0	0	0
T112	12110	0	0	0
T113	8592	0	0	0
T114	11961	0	0	0
T115	20865	0	0	0
T116	11350	0	0	0
T143	0	95	0	0
T151	0	65	0	0
T243	0	116	0	0
T263	0	107	0	0
T282	0	65	0	0
T335	0	293	0	0
T336	0	45	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480779676	2630	0	0
T14	736216	110	0	0
T19	0	61	0	0
T22	0	47	0	0
T30	531275	0	0	0
T31	72855	0	0	0
T57	136352	0	0	0
T65	13528	0	0	0
T112	12110	0	0	0
T113	8592	0	0	0
T114	11961	0	0	0
T115	20865	0	0	0
T116	11350	0	0	0
T143	0	92	0	0
T151	0	90	0	0
T243	0	135	0	0
T263	0	107	0	0
T282	0	139	0	0
T335	0	353	0	0
T336	0	76	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480779676	3486	0	0
T14	736216	106	0	0
T19	0	90	0	0
T22	0	62	0	0
T30	531275	0	0	0
T31	72855	0	0	0
T57	136352	0	0	0
T65	13528	0	0	0
T112	12110	0	0	0
T113	8592	0	0	0
T114	11961	0	0	0
T115	20865	0	0	0
T116	11350	0	0	0
T143	0	89	0	0
T151	0	63	0	0
T243	0	94	0	0
T263	0	99	0	0
T282	0	130	0	0
T335	0	243	0	0
T336	0	60	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480779676	3585	0	0
T14	736216	102	0	0
T19	0	109	0	0
T22	0	48	0	0
T30	531275	0	0	0
T31	72855	0	0	0
T57	136352	0	0	0
T65	13528	0	0	0
T112	12110	0	0	0
T113	8592	0	0	0
T114	11961	0	0	0
T115	20865	0	0	0
T116	11350	0	0	0
T143	0	86	0	0
T151	0	82	0	0
T243	0	150	0	0
T263	0	73	0	0
T282	0	81	0	0
T335	0	262	0	0
T336	0	46	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480779676	2372	0	0
T14	736216	86	0	0
T19	0	103	0	0
T22	0	46	0	0
T30	531275	0	0	0
T31	72855	0	0	0
T57	136352	0	0	0
T65	13528	0	0	0
T112	12110	0	0	0
T113	8592	0	0	0
T114	11961	0	0	0
T115	20865	0	0	0
T116	11350	0	0	0
T143	0	75	0	0
T151	0	84	0	0
T243	0	139	0	0
T263	0	81	0	0
T282	0	127	0	0
T335	0	307	0	0
T336	0	73	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480779676	2223	0	0
T14	736216	80	0	0
T19	0	102	0	0
T22	0	87	0	0
T30	531275	0	0	0
T31	72855	0	0	0
T57	136352	0	0	0
T65	13528	0	0	0
T112	12110	0	0	0
T113	8592	0	0	0
T114	11961	0	0	0
T115	20865	0	0	0
T116	11350	0	0	0
T143	0	111	0	0
T151	0	50	0	0
T243	0	147	0	0
T263	0	141	0	0
T282	0	132	0	0
T335	0	363	0	0
T336	0	57	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480779676	1240	0	0
T14	736216	44	0	0
T19	0	126	0	0
T22	0	25	0	0
T30	531275	0	0	0
T31	72855	0	0	0
T57	136352	0	0	0
T65	13528	0	0	0
T112	12110	0	0	0
T113	8592	0	0	0
T114	11961	0	0	0
T115	20865	0	0	0
T116	11350	0	0	0
T143	0	51	0	0
T151	0	38	0	0
T243	0	102	0	0
T263	0	36	0	0
T282	0	34	0	0
T335	0	193	0	0
T336	0	32	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480779676	1558	0	0
T14	736216	109	0	0
T19	0	103	0	0
T22	0	8	0	0
T30	531275	0	0	0
T31	72855	0	0	0
T57	136352	0	0	0
T65	13528	0	0	0
T112	12110	0	0	0
T113	8592	0	0	0
T114	11961	0	0	0
T115	20865	0	0	0
T116	11350	0	0	0
T143	0	54	0	0
T151	0	48	0	0
T243	0	128	0	0
T263	0	87	0	0
T282	0	46	0	0
T335	0	213	0	0
T336	0	45	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480779676	3538	0	0
T14	736216	101	0	0
T19	0	108	0	0
T22	0	45	0	0
T30	531275	0	0	0
T31	72855	0	0	0
T57	136352	0	0	0
T65	13528	0	0	0
T112	12110	0	0	0
T113	8592	0	0	0
T114	11961	0	0	0
T115	20865	0	0	0
T116	11350	0	0	0
T143	0	73	0	0
T151	0	78	0	0
T243	0	146	0	0
T263	0	147	0	0
T282	0	60	0	0
T335	0	275	0	0
T336	0	57	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480779676	4490	0	0
T14	736216	63	0	0
T15	0	13	0	0
T19	0	134	0	0
T22	0	106	0	0
T30	531275	0	0	0
T31	72855	0	0	0
T57	136352	0	0	0
T65	13528	0	0	0
T83	0	21	0	0
T112	12110	0	0	0
T113	8592	0	0	0
T114	11961	0	0	0
T115	20865	0	0	0
T116	11350	0	0	0
T133	0	23	0	0
T143	0	103	0	0
T151	0	140	0	0
T243	0	140	0	0
T270	0	10	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480779676	2289	0	0
T14	736216	65	0	0
T19	0	75	0	0
T22	0	44	0	0
T30	531275	0	0	0
T31	72855	0	0	0
T57	136352	0	0	0
T65	13528	0	0	0
T112	12110	0	0	0
T113	8592	0	0	0
T114	11961	0	0	0
T115	20865	0	0	0
T116	11350	0	0	0
T143	0	86	0	0
T151	0	82	0	0
T243	0	133	0	0
T263	0	128	0	0
T282	0	128	0	0
T335	0	243	0	0
T336	0	74	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480779676	2605	0	0
T14	736216	87	0	0
T19	0	112	0	0
T22	0	66	0	0
T30	531275	0	0	0
T31	72855	0	0	0
T57	136352	0	0	0
T65	13528	0	0	0
T112	12110	0	0	0
T113	8592	0	0	0
T114	11961	0	0	0
T115	20865	0	0	0
T116	11350	0	0	0
T143	0	106	0	0
T151	0	103	0	0
T243	0	188	0	0
T263	0	139	0	0
T282	0	107	0	0
T335	0	300	0	0
T336	0	63	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480779676	2319	0	0
T14	736216	83	0	0
T19	0	64	0	0
T22	0	56	0	0
T30	531275	0	0	0
T31	72855	0	0	0
T57	136352	0	0	0
T65	13528	0	0	0
T112	12110	0	0	0
T113	8592	0	0	0
T114	11961	0	0	0
T115	20865	0	0	0
T116	11350	0	0	0
T143	0	58	0	0
T151	0	98	0	0
T243	0	101	0	0
T263	0	97	0	0
T282	0	119	0	0
T335	0	287	0	0
T336	0	89	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480779676	2309	0	0
T14	736216	109	0	0
T19	0	72	0	0
T22	0	93	0	0
T30	531275	0	0	0
T31	72855	0	0	0
T57	136352	0	0	0
T65	13528	0	0	0
T112	12110	0	0	0
T113	8592	0	0	0
T114	11961	0	0	0
T115	20865	0	0	0
T116	11350	0	0	0
T143	0	88	0	0
T151	0	70	0	0
T243	0	144	0	0
T263	0	110	0	0
T282	0	89	0	0
T335	0	178	0	0
T336	0	78	0	0