Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_unbuf_err_code_cg_wrap::unbuf_err_code

Group : otp_ctrl_env_pkg::otp_ctrl_unbuf_err_code_cg_wrap::unbuf_err_code_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
85.71	80.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

5 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
unbuf_err_code_cg_wrap[OtpVendorTestErrIdx]	57.14	1	100	1	64	64
unbuf_err_code_cg_wrap[OtpCreatorSwCfgErrIdx]	85.71	1	100	1	64	64
unbuf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]	85.71	1	100	1	64	64
unbuf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]	85.71	1	100	1	64	64
unbuf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]	85.71	1	100	1	64	64

Group Instance : unbuf_err_code_cg_wrap[OtpVendorTestErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
57.14	1	100	1	64	64

Summary for Group Instance unbuf_err_code_cg_wrap[OtpVendorTestErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	3	4	57.14

Variables for Group Instance unbuf_err_code_cg_wrap[OtpVendorTestErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	3	4	57.14	100	1	1	0

Group Instance : unbuf_err_code_cg_wrap[OtpCreatorSwCfgErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.71	1	100	1	64	64

Summary for Group Instance unbuf_err_code_cg_wrap[OtpCreatorSwCfgErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	1	6	85.71

Variables for Group Instance unbuf_err_code_cg_wrap[OtpCreatorSwCfgErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0

Group Instance : unbuf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.71	1	100	1	64	64

Summary for Group Instance unbuf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	1	6	85.71

Variables for Group Instance unbuf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0

Group Instance : unbuf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.71	1	100	1	64	64

Summary for Group Instance unbuf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	1	6	85.71

Variables for Group Instance unbuf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0

Group Instance : unbuf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.71	1	100	1	64	64

Summary for Group Instance unbuf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	1	6	85.71

Variables for Group Instance unbuf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	3	4	57.14

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
ecc_uncorr_err	0	1	1
ecc_corr_err	0	1	1
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
fsm_err	117998	1		T2	429	T3	748	T4	383
check_fail	3	1		T75	1	T156	1	T157	1
access_err	48385	1		T3	88	T4	169	T5	22
no_err	101933	1		T2	49	T3	194	T4	76

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
fsm_err	117404	1		T2	429	T3	748	T4	383
check_fail	1	1		T149	1	-	-	-	-
access_err	48457	1		T2	32	T3	145	T4	119
ecc_uncorr_err	698	1		T108	47	T115	1	T155	6
ecc_corr_err	869	1		T38	4	T28	67	T44	30
no_err	100877	1		T2	17	T3	137	T4	126

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
fsm_err	117718	1		T2	429	T3	748	T4	383
check_fail	2	1		T156	1	T157	1	-	-
access_err	48827	1		T2	22	T3	90	T4	69
ecc_uncorr_err	407	1		T155	7	T179	1	T181	1
ecc_corr_err	1065	1		T26	40	T38	24	T155	3
no_err	100204	1		T2	27	T3	191	T4	176

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
fsm_err	117619	1		T2	429	T3	748	T4	383
check_fail	3	1		T75	1	T149	1	T156	1
access_err	50098	1		T2	17	T3	149	T4	106
ecc_uncorr_err	486	1		T158	1	T178	1	T212	1
ecc_corr_err	1224	1		T26	35	T38	41	T155	2
no_err	98690	1		T2	32	T3	131	T4	139

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
fsm_err	117185	1		T2	429	T3	748	T4	383
check_fail	3	1		T75	1	T149	1	T157	1
access_err	47477	1		T3	66	T4	171	T5	12
ecc_uncorr_err	936	1		T8	1	T108	66	T105	267
ecc_corr_err	966	1		T26	32	T28	52	T58	14
no_err	101492	1		T2	49	T3	214	T4	74