Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

24445621

1

T1

1189

T2

4350

T3

220180

full_word

8010173

1

T1

172

T2

3835

T3

62053

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32455524	1			T1	1361		T2	8185		T3	282233
auto[TlIntgErrCmd]	90	1			T256	2		T257	8		T258	4
auto[TlIntgErrData]	87	1			T256	2		T257	2		T258	1
auto[TlIntgErrBoth]	93	1			T256	6		T258	5		T332	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9615912

1

T1

1167

T2

7421

T3

58192

auto[1]

22839882

1

T1

194

T2

764

T3

224041

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6127793	1			T1	1078		T2	3865		T3	38190
auto[TlIntgErrNone]	partial	auto[1]	18317584	1			T1	111		T2	485		T3	181990
auto[TlIntgErrNone]	full_word	auto[0]	3487995	1			T1	89		T2	3556		T3	20002
auto[TlIntgErrNone]	full_word	auto[1]	4522152	1			T1	83		T2	279		T3	42051
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T256	1		T257	3		T258	3
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T257	5		T258	1		T332	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T339	1		T340	1		T341	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T256	1		T333	1		-	-
auto[TlIntgErrData]	partial	auto[0]	37	1			T256	1		T258	1		T332	1
auto[TlIntgErrData]	partial	auto[1]	40	1			T257	1		T332	6		T333	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T332	2		T339	1		T342	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T256	1		T257	1		T332	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1			T256	2		T258	1		T332	3
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T256	3		T258	3		T332	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T258	1		T333	1		T340	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T256	1		T343	1		T335	1