Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.20		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	446890331	7740350	0	0
check_regwen_rd_A	446890331	2708	0	0
check_timeout_rd_A	446890331	2631	0	0
check_trigger_regwen_rd_A	446890331	2598	0	0
consistency_check_period_rd_A	446890331	3065	0	0
creator_sw_cfg_read_lock_rd_A	446890331	2736	0	0
direct_access_address_rd_A	446890331	2253	0	0
direct_access_wdata_0_rd_A	446890331	1131	0	0
direct_access_wdata_1_rd_A	446890331	1342	0	0
integrity_check_period_rd_A	446890331	2673	0	0
intr_enable_rd_A	446890331	3681	0	0
owner_sw_cfg_read_lock_rd_A	446890331	2520	0	0
rot_creator_auth_codesign_read_lock_rd_A	446890331	2578	0	0
rot_creator_auth_state_read_lock_rd_A	446890331	2324	0	0
vendor_test_read_lock_rd_A	446890331	2368	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446890331	7740350	0	0
T3	611023	81011	0	0
T4	674981	73348	0	0
T5	45673	0	0	0
T6	794691	238046	0	0
T7	10616	0	0	0
T8	11696	0	0	0
T9	13753	0	0	0
T10	5189	0	0	0
T11	26726	0	0	0
T12	0	42444	0	0
T14	0	30674	0	0
T16	0	314299	0	0
T26	68242	0	0	0
T37	0	10128	0	0
T137	0	211402	0	0
T144	0	68027	0	0
T239	0	46188	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446890331	2708	0	0
T14	211559	70	0	0
T16	127186	0	0	0
T28	137846	0	0	0
T37	362535	0	0	0
T96	0	31	0	0
T137	0	208	0	0
T142	33176	0	0	0
T144	280194	0	0	0
T160	10173	0	0	0
T176	0	31	0	0
T193	15817	0	0	0
T194	79131	0	0	0
T195	24137	0	0	0
T266	0	134	0	0
T312	0	70	0	0
T313	0	49	0	0
T314	0	33	0	0
T315	0	28	0	0
T316	0	60	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446890331	2631	0	0
T14	211559	66	0	0
T16	127186	0	0	0
T28	137846	0	0	0
T37	362535	0	0	0
T96	0	65	0	0
T137	0	283	0	0
T142	33176	0	0	0
T144	280194	0	0	0
T160	10173	0	0	0
T176	0	59	0	0
T193	15817	0	0	0
T194	79131	0	0	0
T195	24137	0	0	0
T266	0	151	0	0
T312	0	53	0	0
T313	0	74	0	0
T314	0	5	0	0
T315	0	50	0	0
T316	0	41	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446890331	2598	0	0
T14	211559	40	0	0
T16	127186	0	0	0
T28	137846	0	0	0
T37	362535	0	0	0
T96	0	65	0	0
T137	0	200	0	0
T142	33176	0	0	0
T144	280194	0	0	0
T160	10173	0	0	0
T176	0	23	0	0
T193	15817	0	0	0
T194	79131	0	0	0
T195	24137	0	0	0
T266	0	91	0	0
T312	0	61	0	0
T313	0	44	0	0
T314	0	25	0	0
T315	0	49	0	0
T316	0	19	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446890331	3065	0	0
T14	211559	49	0	0
T16	127186	0	0	0
T28	137846	0	0	0
T37	362535	0	0	0
T96	0	72	0	0
T137	0	283	0	0
T142	33176	0	0	0
T144	280194	0	0	0
T160	10173	0	0	0
T176	0	58	0	0
T193	15817	0	0	0
T194	79131	0	0	0
T195	24137	0	0	0
T266	0	108	0	0
T312	0	58	0	0
T313	0	78	0	0
T314	0	31	0	0
T315	0	46	0	0
T316	0	52	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446890331	2736	0	0
T14	211559	71	0	0
T16	127186	0	0	0
T28	137846	0	0	0
T37	362535	0	0	0
T96	0	94	0	0
T137	0	255	0	0
T142	33176	0	0	0
T144	280194	0	0	0
T160	10173	0	0	0
T176	0	94	0	0
T193	15817	0	0	0
T194	79131	0	0	0
T195	24137	0	0	0
T266	0	133	0	0
T312	0	48	0	0
T313	0	91	0	0
T314	0	27	0	0
T315	0	23	0	0
T316	0	74	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446890331	2253	0	0
T14	211559	45	0	0
T16	127186	0	0	0
T28	137846	0	0	0
T37	362535	0	0	0
T96	0	79	0	0
T137	0	244	0	0
T142	33176	0	0	0
T144	280194	0	0	0
T160	10173	0	0	0
T176	0	51	0	0
T193	15817	0	0	0
T194	79131	0	0	0
T195	24137	0	0	0
T266	0	205	0	0
T312	0	82	0	0
T313	0	94	0	0
T314	0	3	0	0
T315	0	51	0	0
T316	0	50	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446890331	1131	0	0
T14	211559	18	0	0
T16	127186	0	0	0
T28	137846	0	0	0
T37	362535	0	0	0
T96	0	29	0	0
T137	0	203	0	0
T142	33176	0	0	0
T144	280194	0	0	0
T160	10173	0	0	0
T176	0	24	0	0
T193	15817	0	0	0
T194	79131	0	0	0
T195	24137	0	0	0
T266	0	44	0	0
T312	0	16	0	0
T313	0	46	0	0
T314	0	38	0	0
T315	0	31	0	0
T316	0	17	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446890331	1342	0	0
T14	211559	11	0	0
T16	127186	0	0	0
T28	137846	0	0	0
T37	362535	0	0	0
T96	0	65	0	0
T137	0	263	0	0
T142	33176	0	0	0
T144	280194	0	0	0
T160	10173	0	0	0
T176	0	57	0	0
T193	15817	0	0	0
T194	79131	0	0	0
T195	24137	0	0	0
T266	0	71	0	0
T312	0	35	0	0
T313	0	26	0	0
T314	0	20	0	0
T315	0	37	0	0
T316	0	28	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446890331	2673	0	0
T14	211559	45	0	0
T16	127186	0	0	0
T28	137846	0	0	0
T37	362535	0	0	0
T96	0	66	0	0
T137	0	216	0	0
T142	33176	0	0	0
T144	280194	0	0	0
T160	10173	0	0	0
T176	0	42	0	0
T193	15817	0	0	0
T194	79131	0	0	0
T195	24137	0	0	0
T266	0	120	0	0
T312	0	63	0	0
T313	0	91	0	0
T314	0	17	0	0
T315	0	24	0	0
T316	0	45	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446890331	3681	0	0
T14	211559	83	0	0
T16	127186	0	0	0
T28	137846	0	0	0
T37	362535	0	0	0
T71	0	22	0	0
T96	0	67	0	0
T109	0	20	0	0
T137	0	244	0	0
T142	33176	0	0	0
T144	280194	0	0	0
T160	10173	0	0	0
T193	15817	0	0	0
T194	79131	0	0	0
T195	24137	0	0	0
T197	0	27	0	0
T266	0	163	0	0
T310	0	33	0	0
T312	0	61	0	0
T313	0	92	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446890331	2520	0	0
T14	211559	54	0	0
T16	127186	0	0	0
T28	137846	0	0	0
T37	362535	0	0	0
T96	0	75	0	0
T137	0	238	0	0
T142	33176	0	0	0
T144	280194	0	0	0
T160	10173	0	0	0
T176	0	50	0	0
T193	15817	0	0	0
T194	79131	0	0	0
T195	24137	0	0	0
T266	0	130	0	0
T312	0	56	0	0
T313	0	60	0	0
T314	0	43	0	0
T315	0	40	0	0
T316	0	28	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446890331	2578	0	0
T14	211559	29	0	0
T16	127186	0	0	0
T28	137846	0	0	0
T37	362535	0	0	0
T96	0	48	0	0
T137	0	209	0	0
T142	33176	0	0	0
T144	280194	0	0	0
T160	10173	0	0	0
T176	0	30	0	0
T193	15817	0	0	0
T194	79131	0	0	0
T195	24137	0	0	0
T266	0	124	0	0
T312	0	98	0	0
T313	0	60	0	0
T314	0	44	0	0
T315	0	34	0	0
T316	0	32	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446890331	2324	0	0
T14	211559	59	0	0
T16	127186	0	0	0
T28	137846	0	0	0
T37	362535	0	0	0
T96	0	61	0	0
T137	0	217	0	0
T142	33176	0	0	0
T144	280194	0	0	0
T160	10173	0	0	0
T176	0	31	0	0
T193	15817	0	0	0
T194	79131	0	0	0
T195	24137	0	0	0
T266	0	101	0	0
T312	0	51	0	0
T313	0	74	0	0
T314	0	18	0	0
T315	0	38	0	0
T316	0	65	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446890331	2368	0	0
T14	211559	41	0	0
T16	127186	0	0	0
T28	137846	0	0	0
T37	362535	0	0	0
T96	0	63	0	0
T137	0	250	0	0
T142	33176	0	0	0
T144	280194	0	0	0
T160	10173	0	0	0
T176	0	50	0	0
T193	15817	0	0	0
T194	79131	0	0	0
T195	24137	0	0	0
T266	0	89	0	0
T312	0	35	0	0
T313	0	49	0	0
T314	0	46	0	0
T315	0	33	0	0
T316	0	28	0	0