Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.19	94.16	96.15	97.02		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.19	94.16	96.15	97.02		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T71,T72,T164

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T76,T32,T113

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T15,T16,T17

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T81,T152,T165
1	Covered	T81,T152,T165

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T10,T21

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T10,T21

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T4
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T2,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T4,T6
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T70,T117,T119
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T2,T69,T187
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T3,T4
ReadSt->ReadWaitSt	252	Covered	T2,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T170,T173,T193
ReadWaitSt->IdleSt	270	Covered	T2,T3,T4
ResetSt->ErrorSt	315	Covered	T79,T80,T81
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T3,T4
CheckFailError	317	Covered	T81,T152,T165
FsmStateError	289	Covered	T1,T2,T4
MacroEccCorrError	221	Covered	T71,T76,T32
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T1,T4,T10
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T3,T4
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T81,T152,T165
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T4
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T71,T72,T173
MacroEccCorrError->NoError	235	Covered	T76,T32,T113
NoError->AccessError	256	Covered	T1,T3,T4
NoError->CheckFailError	317	Covered	T81,T152,T165
NoError->FsmStateError	289	Covered	T2,T4,T6
NoError->MacroEccCorrError	221	Covered	T71,T76,T32

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T71,T72,T164
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T208,T209,T210
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T3,T111,T21
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T76,T32,T113
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T170,T173,T193
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T15,T16,T17
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T4,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T4,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T81,T152,T165
1	0	Covered	T81,T152,T165
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	482935496	482080516	0	0
DigestKnown_A	482935496	482080516	0	0
DigestOffsetMustBeRepresentable_A	1152	1152	0	0
EccErrorState_A	482935496	12181	0	0
ErrorKnown_A	482935496	482080516	0	0
FsmStateKnown_A	482935496	482080516	0	0
InitDoneKnown_A	482935496	482080516	0	0
InitReadLocksPartition_A	482935496	90582428	0	0
InitWriteLocksPartition_A	482935496	90582428	0	0
OffsetMustBeBlockAligned_A	1152	1152	0	0
OtpAddrKnown_A	482935496	482080516	0	0
OtpCmdKnown_A	482935496	482080516	0	0
OtpErrorState_A	482935496	40	0	0
OtpReqKnown_A	482935496	482080516	0	0
OtpSizeKnown_A	482935496	482080516	0	0
OtpWdataKnown_A	482935496	482080516	0	0
ReadLockPropagation_A	482935496	214401177	0	0
SizeMustBeBlockAligned_A	1152	1152	0	0
TlulGntKnown_A	482935496	482080516	0	0
TlulRdataKnown_A	482935496	482080516	0	0
TlulReadOnReadLock_A	482935496	8285	0	0
TlulRerrorKnown_A	482935496	482080516	0	0
TlulRvalidKnown_A	482935496	482080516	0	0
WriteLockPropagation_A	482935496	2244190	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	482935496	27137221	0	0
u_state_regs_A	482935496	482080516	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	482080516	0	0
T1	81968	81774	0	0
T2	9861	9591	0	0
T3	623106	623095	0	0
T4	514427	514399	0	0
T5	72843	72145	0	0
T6	43455	43208	0	0
T7	479739	479730	0	0
T8	14970	14698	0	0
T9	6063	5992	0	0
T10	21202	20906	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	482080516	0	0
T1	81968	81774	0	0
T2	9861	9591	0	0
T3	623106	623095	0	0
T4	514427	514399	0	0
T5	72843	72145	0	0
T6	43455	43208	0	0
T7	479739	479730	0	0
T8	14970	14698	0	0
T9	6063	5992	0	0
T10	21202	20906	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	12181	0	0
T81	13243	2295	0	0
T84	197547	0	0	0
T152	0	2931	0	0
T165	0	3100	0	0
T175	0	3855	0	0
T176	14380	0	0	0
T177	6257	0	0	0
T178	113698	0	0	0
T179	37049	0	0	0
T180	13095	0	0	0
T181	12101	0	0	0
T182	8181	0	0	0
T183	4094	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	482080516	0	0
T1	81968	81774	0	0
T2	9861	9591	0	0
T3	623106	623095	0	0
T4	514427	514399	0	0
T5	72843	72145	0	0
T6	43455	43208	0	0
T7	479739	479730	0	0
T8	14970	14698	0	0
T9	6063	5992	0	0
T10	21202	20906	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	482080516	0	0
T1	81968	81774	0	0
T2	9861	9591	0	0
T3	623106	623095	0	0
T4	514427	514399	0	0
T5	72843	72145	0	0
T6	43455	43208	0	0
T7	479739	479730	0	0
T8	14970	14698	0	0
T9	6063	5992	0	0
T10	21202	20906	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	482080516	0	0
T1	81968	81774	0	0
T2	9861	9591	0	0
T3	623106	623095	0	0
T4	514427	514399	0	0
T5	72843	72145	0	0
T6	43455	43208	0	0
T7	479739	479730	0	0
T8	14970	14698	0	0
T9	6063	5992	0	0
T10	21202	20906	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	90582428	0	0
T1	81968	44951	0	0
T2	9861	4564	0	0
T3	623106	1133	0	0
T4	514427	152383	0	0
T5	72843	1048	0	0
T6	43455	26925	0	0
T7	479739	560	0	0
T8	14970	482	0	0
T9	6063	161	0	0
T10	21202	5397	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	90582428	0	0
T1	81968	44951	0	0
T2	9861	4564	0	0
T3	623106	1133	0	0
T4	514427	152383	0	0
T5	72843	1048	0	0
T6	43455	26925	0	0
T7	479739	560	0	0
T8	14970	482	0	0
T9	6063	161	0	0
T10	21202	5397	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	482080516	0	0
T1	81968	81774	0	0
T2	9861	9591	0	0
T3	623106	623095	0	0
T4	514427	514399	0	0
T5	72843	72145	0	0
T6	43455	43208	0	0
T7	479739	479730	0	0
T8	14970	14698	0	0
T9	6063	5992	0	0
T10	21202	20906	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	482080516	0	0
T1	81968	81774	0	0
T2	9861	9591	0	0
T3	623106	623095	0	0
T4	514427	514399	0	0
T5	72843	72145	0	0
T6	43455	43208	0	0
T7	479739	479730	0	0
T8	14970	14698	0	0
T9	6063	5992	0	0
T10	21202	20906	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	40	0	0
T36	11465	0	0	0
T64	805719	0	0	0
T102	0	3	0	0
T108	67819	0	0	0
T170	202244	1	0	0
T173	0	1	0	0
T189	14200	0	0	0
T193	0	1	0	0
T203	13443	0	0	0
T208	0	1	0	0
T209	0	1	0	0
T210	0	1	0	0
T211	0	1	0	0
T212	0	1	0	0
T213	0	1	0	0
T214	21991	0	0	0
T215	31735	0	0	0
T216	21602	0	0	0
T217	10243	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	482080516	0	0
T1	81968	81774	0	0
T2	9861	9591	0	0
T3	623106	623095	0	0
T4	514427	514399	0	0
T5	72843	72145	0	0
T6	43455	43208	0	0
T7	479739	479730	0	0
T8	14970	14698	0	0
T9	6063	5992	0	0
T10	21202	20906	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	482080516	0	0
T1	81968	81774	0	0
T2	9861	9591	0	0
T3	623106	623095	0	0
T4	514427	514399	0	0
T5	72843	72145	0	0
T6	43455	43208	0	0
T7	479739	479730	0	0
T8	14970	14698	0	0
T9	6063	5992	0	0
T10	21202	20906	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	482080516	0	0
T1	81968	81774	0	0
T2	9861	9591	0	0
T3	623106	623095	0	0
T4	514427	514399	0	0
T5	72843	72145	0	0
T6	43455	43208	0	0
T7	479739	479730	0	0
T8	14970	14698	0	0
T9	6063	5992	0	0
T10	21202	20906	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	214401177	0	0
T1	81968	61027	0	0
T2	9861	0	0	0
T3	623106	287459	0	0
T4	514427	156441	0	0
T5	72843	22457	0	0
T6	43455	0	0	0
T7	479739	406447	0	0
T8	14970	0	0	0
T9	6063	0	0	0
T10	21202	11958	0	0
T11	0	703104	0	0
T111	0	275945	0	0
T125	0	1366	0	0
T196	0	44265	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	482080516	0	0
T1	81968	81774	0	0
T2	9861	9591	0	0
T3	623106	623095	0	0
T4	514427	514399	0	0
T5	72843	72145	0	0
T6	43455	43208	0	0
T7	479739	479730	0	0
T8	14970	14698	0	0
T9	6063	5992	0	0
T10	21202	20906	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	482080516	0	0
T1	81968	81774	0	0
T2	9861	9591	0	0
T3	623106	623095	0	0
T4	514427	514399	0	0
T5	72843	72145	0	0
T6	43455	43208	0	0
T7	479739	479730	0	0
T8	14970	14698	0	0
T9	6063	5992	0	0
T10	21202	20906	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	8285	0	0
T1	81968	8	0	0
T2	9861	0	0	0
T3	623106	5	0	0
T4	514427	42	0	0
T5	72843	8	0	0
T6	43455	5	0	0
T7	479739	15	0	0
T8	14970	0	0	0
T9	6063	0	0	0
T10	21202	4	0	0
T11	0	59	0	0
T110	0	5	0	0
T111	0	67	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	482080516	0	0
T1	81968	81774	0	0
T2	9861	9591	0	0
T3	623106	623095	0	0
T4	514427	514399	0	0
T5	72843	72145	0	0
T6	43455	43208	0	0
T7	479739	479730	0	0
T8	14970	14698	0	0
T9	6063	5992	0	0
T10	21202	20906	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	482080516	0	0
T1	81968	81774	0	0
T2	9861	9591	0	0
T3	623106	623095	0	0
T4	514427	514399	0	0
T5	72843	72145	0	0
T6	43455	43208	0	0
T7	479739	479730	0	0
T8	14970	14698	0	0
T9	6063	5992	0	0
T10	21202	20906	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	2244190	0	0
T21	68464	4728	0	0
T22	0	6722	0	0
T31	0	61815	0	0
T64	0	18745	0	0
T70	16529	0	0	0
T76	0	2144	0	0
T105	0	3281	0	0
T106	0	21873	0	0
T107	0	7503	0	0
T109	0	43210	0	0
T115	0	5829	0	0
T116	25793	0	0	0
T117	17796	0	0	0
T118	21823	0	0	0
T119	27020	0	0	0
T120	21008	0	0	0
T121	16679	0	0	0
T122	14300	0	0	0
T135	53931	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	27137221	0	0
T5	72843	21279	0	0
T6	43455	0	0	0
T7	479739	0	0	0
T8	14970	0	0	0
T9	6063	0	0	0
T10	21202	2622	0	0
T11	114571	0	0	0
T21	0	59302	0	0
T22	0	44293	0	0
T31	0	231248	0	0
T32	0	48724	0	0
T69	12016	0	0	0
T76	0	33042	0	0
T105	0	55801	0	0
T106	0	304139	0	0
T110	11959	0	0	0
T111	451402	0	0	0
T123	0	12072	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	482080516	0	0
T1	81968	81774	0	0
T2	9861	9591	0	0
T3	623106	623095	0	0
T4	514427	514399	0	0
T5	72843	72145	0	0
T6	43455	43208	0	0
T7	479739	479730	0	0
T8	14970	14698	0	0
T9	6063	5992	0	0
T10	21202	20906	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T67,T18,T45

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T76,T32,T171

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T15,T16,T17

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T81,T152,T172
1	Covered	T81,T152,T172

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T122,T123

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T122,T123

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T4
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T2,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T4,T6
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T2,T69,T70
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T71,T217,T169
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T3,T4
ReadSt->ReadWaitSt	252	Covered	T2,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T158,T218,T219
ReadWaitSt->IdleSt	270	Covered	T2,T3,T4
ResetSt->ErrorSt	315	Covered	T79,T80,T81
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T3,T4
CheckFailError	317	Covered	T81,T152,T172
FsmStateError	289	Covered	T1,T2,T4
MacroEccCorrError	221	Covered	T67,T76,T32
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T1,T4,T10
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T3,T4,T5
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T81,T152,T172
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T4
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T67,T171,T18
MacroEccCorrError->NoError	235	Covered	T76,T32,T174
NoError->AccessError	256	Covered	T1,T3,T4
NoError->CheckFailError	317	Covered	T81,T152,T172
NoError->FsmStateError	289	Covered	T2,T4,T6
NoError->MacroEccCorrError	221	Covered	T67,T76,T32

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T122,T123
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T67,T18,T45
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T71,T217,T169
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T7,T11,T106
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T76,T32,T171
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T158,T218,T219
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T15,T16,T17
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T4,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T4,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T81,T152,T172
1	0	Covered	T81,T152,T172
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	482935496	482080516	0	0
DigestKnown_A	482935496	482080516	0	0
DigestOffsetMustBeRepresentable_A	1152	1152	0	0
EccErrorState_A	482935496	16167	0	0
ErrorKnown_A	482935496	482080516	0	0
FsmStateKnown_A	482935496	482080516	0	0
InitDoneKnown_A	482935496	482080516	0	0
InitReadLocksPartition_A	482935496	90761120	0	0
InitWriteLocksPartition_A	482935496	90761120	0	0
OffsetMustBeBlockAligned_A	1152	1152	0	0
OtpAddrKnown_A	482935496	482080516	0	0
OtpCmdKnown_A	482935496	482080516	0	0
OtpErrorState_A	482935496	40	0	0
OtpReqKnown_A	482935496	482080516	0	0
OtpSizeKnown_A	482935496	482080516	0	0
OtpWdataKnown_A	482935496	482080516	0	0
ReadLockPropagation_A	482935496	216521803	0	0
SizeMustBeBlockAligned_A	1152	1152	0	0
TlulGntKnown_A	482935496	482080516	0	0
TlulRdataKnown_A	482935496	482080516	0	0
TlulReadOnReadLock_A	482935496	7979	0	0
TlulRerrorKnown_A	482935496	482080516	0	0
TlulRvalidKnown_A	482935496	482080516	0	0
WriteLockPropagation_A	482935496	606698	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	482935496	9558502	0	0
u_state_regs_A	482935496	482080516	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	482080516	0	0
T1	81968	81774	0	0
T2	9861	9591	0	0
T3	623106	623095	0	0
T4	514427	514399	0	0
T5	72843	72145	0	0
T6	43455	43208	0	0
T7	479739	479730	0	0
T8	14970	14698	0	0
T9	6063	5992	0	0
T10	21202	20906	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	482080516	0	0
T1	81968	81774	0	0
T2	9861	9591	0	0
T3	623106	623095	0	0
T4	514427	514399	0	0
T5	72843	72145	0	0
T6	43455	43208	0	0
T7	479739	479730	0	0
T8	14970	14698	0	0
T9	6063	5992	0	0
T10	21202	20906	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	16167	0	0
T81	13243	2295	0	0
T84	197547	0	0	0
T152	0	2931	0	0
T165	0	3100	0	0
T166	0	3886	0	0
T172	0	3955	0	0
T176	14380	0	0	0
T177	6257	0	0	0
T178	113698	0	0	0
T179	37049	0	0	0
T180	13095	0	0	0
T181	12101	0	0	0
T182	8181	0	0	0
T183	4094	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	482080516	0	0
T1	81968	81774	0	0
T2	9861	9591	0	0
T3	623106	623095	0	0
T4	514427	514399	0	0
T5	72843	72145	0	0
T6	43455	43208	0	0
T7	479739	479730	0	0
T8	14970	14698	0	0
T9	6063	5992	0	0
T10	21202	20906	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	482080516	0	0
T1	81968	81774	0	0
T2	9861	9591	0	0
T3	623106	623095	0	0
T4	514427	514399	0	0
T5	72843	72145	0	0
T6	43455	43208	0	0
T7	479739	479730	0	0
T8	14970	14698	0	0
T9	6063	5992	0	0
T10	21202	20906	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	482080516	0	0
T1	81968	81774	0	0
T2	9861	9591	0	0
T3	623106	623095	0	0
T4	514427	514399	0	0
T5	72843	72145	0	0
T6	43455	43208	0	0
T7	479739	479730	0	0
T8	14970	14698	0	0
T9	6063	5992	0	0
T10	21202	20906	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	90761120	0	0
T1	81968	44985	0	0
T2	9861	4598	0	0
T3	623106	1235	0	0
T4	514427	152404	0	0
T5	72843	1218	0	0
T6	43455	26976	0	0
T7	479739	662	0	0
T8	14970	516	0	0
T9	6063	178	0	0
T10	21202	5465	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	90761120	0	0
T1	81968	44985	0	0
T2	9861	4598	0	0
T3	623106	1235	0	0
T4	514427	152404	0	0
T5	72843	1218	0	0
T6	43455	26976	0	0
T7	479739	662	0	0
T8	14970	516	0	0
T9	6063	178	0	0
T10	21202	5465	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	482080516	0	0
T1	81968	81774	0	0
T2	9861	9591	0	0
T3	623106	623095	0	0
T4	514427	514399	0	0
T5	72843	72145	0	0
T6	43455	43208	0	0
T7	479739	479730	0	0
T8	14970	14698	0	0
T9	6063	5992	0	0
T10	21202	20906	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	482080516	0	0
T1	81968	81774	0	0
T2	9861	9591	0	0
T3	623106	623095	0	0
T4	514427	514399	0	0
T5	72843	72145	0	0
T6	43455	43208	0	0
T7	479739	479730	0	0
T8	14970	14698	0	0
T9	6063	5992	0	0
T10	21202	20906	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	40	0	0
T32	67403	0	0	0
T71	10901	1	0	0
T76	42608	0	0	0
T106	563552	0	0	0
T112	60627	0	0	0
T158	0	1	0	0
T162	464012	0	0	0
T163	388246	0	0	0
T164	0	1	0	0
T169	0	1	0	0
T185	16710	0	0	0
T186	13138	0	0	0
T187	10425	0	0	0
T217	0	1	0	0
T218	0	1	0	0
T220	0	1	0	0
T221	0	1	0	0
T222	0	1	0	0
T223	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	482080516	0	0
T1	81968	81774	0	0
T2	9861	9591	0	0
T3	623106	623095	0	0
T4	514427	514399	0	0
T5	72843	72145	0	0
T6	43455	43208	0	0
T7	479739	479730	0	0
T8	14970	14698	0	0
T9	6063	5992	0	0
T10	21202	20906	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	482080516	0	0
T1	81968	81774	0	0
T2	9861	9591	0	0
T3	623106	623095	0	0
T4	514427	514399	0	0
T5	72843	72145	0	0
T6	43455	43208	0	0
T7	479739	479730	0	0
T8	14970	14698	0	0
T9	6063	5992	0	0
T10	21202	20906	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	482080516	0	0
T1	81968	81774	0	0
T2	9861	9591	0	0
T3	623106	623095	0	0
T4	514427	514399	0	0
T5	72843	72145	0	0
T6	43455	43208	0	0
T7	479739	479730	0	0
T8	14970	14698	0	0
T9	6063	5992	0	0
T10	21202	20906	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	216521803	0	0
T1	81968	61008	0	0
T2	9861	0	0	0
T3	623106	287576	0	0
T4	514427	157646	0	0
T5	72843	18754	0	0
T6	43455	0	0	0
T7	479739	405759	0	0
T8	14970	0	0	0
T9	6063	0	0	0
T10	21202	11945	0	0
T11	0	704063	0	0
T21	0	2557	0	0
T111	0	274413	0	0
T196	0	44263	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	482080516	0	0
T1	81968	81774	0	0
T2	9861	9591	0	0
T3	623106	623095	0	0
T4	514427	514399	0	0
T5	72843	72145	0	0
T6	43455	43208	0	0
T7	479739	479730	0	0
T8	14970	14698	0	0
T9	6063	5992	0	0
T10	21202	20906	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	482080516	0	0
T1	81968	81774	0	0
T2	9861	9591	0	0
T3	623106	623095	0	0
T4	514427	514399	0	0
T5	72843	72145	0	0
T6	43455	43208	0	0
T7	479739	479730	0	0
T8	14970	14698	0	0
T9	6063	5992	0	0
T10	21202	20906	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	7979	0	0
T1	81968	4	0	0
T2	9861	0	0	0
T3	623106	1	0	0
T4	514427	49	0	0
T5	72843	3	0	0
T6	43455	4	0	0
T7	479739	11	0	0
T8	14970	0	0	0
T9	6063	0	0	0
T10	21202	4	0	0
T11	0	60	0	0
T110	0	4	0	0
T111	0	61	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	482080516	0	0
T1	81968	81774	0	0
T2	9861	9591	0	0
T3	623106	623095	0	0
T4	514427	514399	0	0
T5	72843	72145	0	0
T6	43455	43208	0	0
T7	479739	479730	0	0
T8	14970	14698	0	0
T9	6063	5992	0	0
T10	21202	20906	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	482080516	0	0
T1	81968	81774	0	0
T2	9861	9591	0	0
T3	623106	623095	0	0
T4	514427	514399	0	0
T5	72843	72145	0	0
T6	43455	43208	0	0
T7	479739	479730	0	0
T8	14970	14698	0	0
T9	6063	5992	0	0
T10	21202	20906	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	606698	0	0
T23	0	14132	0	0
T32	67403	0	0	0
T64	0	4459	0	0
T72	14065	0	0	0
T76	42608	2785	0	0
T106	563552	7199	0	0
T112	60627	11058	0	0
T114	0	4223	0	0
T115	0	2679	0	0
T136	0	5600	0	0
T163	388246	0	0	0
T171	99462	0	0	0
T186	13138	0	0	0
T187	10425	0	0	0
T200	0	15992	0	0
T224	0	2758	0	0
T225	32254	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	9558502	0	0
T10	21202	2588	0	0
T11	114571	0	0	0
T29	14537	0	0	0
T32	0	58514	0	0
T35	55995	0	0	0
T64	0	54106	0	0
T69	12016	0	0	0
T76	0	32940	0	0
T106	0	177639	0	0
T107	0	57489	0	0
T110	11959	0	0	0
T111	451402	0	0	0
T112	0	45708	0	0
T122	0	6854	0	0
T123	0	12021	0	0
T125	52976	0	0	0
T196	52994	0	0	0
T201	6697	0	0	0
T214	0	2435	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482935496	482080516	0	0
T1	81968	81774	0	0
T2	9861	9591	0	0
T3	623106	623095	0	0
T4	514427	514399	0	0
T5	72843	72145	0	0
T6	43455	43208	0	0
T7	479739	479730	0	0
T8	14970	14698	0	0
T9	6063	5992	0	0
T10	21202	20906	0	0