Group : dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg
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Group : dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 98.53 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv

34 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
status_csr_cg::OtpBusIntegErrorIdx 50.00 1 100 1 64 64
lc_prog_cg 100.00 1 100 1 64 64
otbn_req_cg 100.00 1 100 1 64 64
status_csr_cg::OtpCheckPendingIdx 100.00 1 100 1 64 64
status_csr_cg::OtpCreatorSwCfgErrIdx 100.00 1 100 1 64 64
status_csr_cg::OtpDaiErrIdx 100.00 1 100 1 64 64
status_csr_cg::OtpDaiIdleIdx 100.00 1 100 1 64 64
status_csr_cg::OtpDerivKeyFsmErrIdx 100.00 1 100 1 64 64
status_csr_cg::OtpHwCfg0ErrIdx 100.00 1 100 1 64 64
status_csr_cg::OtpHwCfg1ErrIdx 100.00 1 100 1 64 64
status_csr_cg::OtpLciErrIdx 100.00 1 100 1 64 64
status_csr_cg::OtpLfsrFsmErrIdx 100.00 1 100 1 64 64
status_csr_cg::OtpLifeCycleErrIdx 100.00 1 100 1 64 64
status_csr_cg::OtpOwnerSwCfgErrIdx 100.00 1 100 1 64 64
status_csr_cg::OtpRotCreatorAuthCodesignErrIdx 100.00 1 100 1 64 64
status_csr_cg::OtpRotCreatorAuthStateErrIdx 100.00 1 100 1 64 64
status_csr_cg::OtpScramblingFsmErrIdx 100.00 1 100 1 64 64
status_csr_cg::OtpSecret0ErrIdx 100.00 1 100 1 64 64
status_csr_cg::OtpSecret1ErrIdx 100.00 1 100 1 64 64
status_csr_cg::OtpSecret2ErrIdx 100.00 1 100 1 64 64
status_csr_cg::OtpTimeoutErrIdx 100.00 1 100 1 64 64
status_csr_cg::OtpVendorTestErrIdx 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::PutFullData_mask_not_match_size 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::addr_not_align_mask 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::addr_not_align_size 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::invalid_a_opcode 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::mask_not_in_enabled_lanes 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::size_over_max 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::PutFullData_mask_not_match_size 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::addr_not_align_mask 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::addr_not_align_size 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::invalid_a_opcode 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::mask_not_in_enabled_lanes 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::size_over_max 100.00 1 100 1 64 64




Group Instance : status_csr_cg::OtpBusIntegErrorIdx
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance status_csr_cg::OtpBusIntegErrorIdx

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 3 1 50.00


Variables for Group Instance status_csr_cg::OtpBusIntegErrorIdx
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 2 0 0.00 100 0 1 0
cp_value 2 1 1 50.00 100 1 1 2



Group Instance : lc_prog_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lc_prog_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance lc_prog_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 0 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : otbn_req_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otbn_req_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance otbn_req_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 0 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : status_csr_cg::OtpCheckPendingIdx
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance status_csr_cg::OtpCheckPendingIdx

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance status_csr_cg::OtpCheckPendingIdx
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 0 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : status_csr_cg::OtpCreatorSwCfgErrIdx
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance status_csr_cg::OtpCreatorSwCfgErrIdx

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance status_csr_cg::OtpCreatorSwCfgErrIdx
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 0 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : status_csr_cg::OtpDaiErrIdx
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance status_csr_cg::OtpDaiErrIdx

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance status_csr_cg::OtpDaiErrIdx
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 0 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : status_csr_cg::OtpDaiIdleIdx
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance status_csr_cg::OtpDaiIdleIdx

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance status_csr_cg::OtpDaiIdleIdx
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 0 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : status_csr_cg::OtpDerivKeyFsmErrIdx
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance status_csr_cg::OtpDerivKeyFsmErrIdx

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance status_csr_cg::OtpDerivKeyFsmErrIdx
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 0 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : status_csr_cg::OtpHwCfg0ErrIdx
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance status_csr_cg::OtpHwCfg0ErrIdx

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance status_csr_cg::OtpHwCfg0ErrIdx
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 0 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : status_csr_cg::OtpHwCfg1ErrIdx
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance status_csr_cg::OtpHwCfg1ErrIdx

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance status_csr_cg::OtpHwCfg1ErrIdx
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 0 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : status_csr_cg::OtpLciErrIdx
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance status_csr_cg::OtpLciErrIdx

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance status_csr_cg::OtpLciErrIdx
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 0 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : status_csr_cg::OtpLfsrFsmErrIdx
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance status_csr_cg::OtpLfsrFsmErrIdx

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance status_csr_cg::OtpLfsrFsmErrIdx
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 0 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : status_csr_cg::OtpLifeCycleErrIdx
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance status_csr_cg::OtpLifeCycleErrIdx

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance status_csr_cg::OtpLifeCycleErrIdx
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 0 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : status_csr_cg::OtpOwnerSwCfgErrIdx
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance status_csr_cg::OtpOwnerSwCfgErrIdx

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance status_csr_cg::OtpOwnerSwCfgErrIdx
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 0 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : status_csr_cg::OtpRotCreatorAuthCodesignErrIdx
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance status_csr_cg::OtpRotCreatorAuthCodesignErrIdx

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance status_csr_cg::OtpRotCreatorAuthCodesignErrIdx
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 0 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : status_csr_cg::OtpRotCreatorAuthStateErrIdx
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance status_csr_cg::OtpRotCreatorAuthStateErrIdx

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance status_csr_cg::OtpRotCreatorAuthStateErrIdx
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 0 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : status_csr_cg::OtpScramblingFsmErrIdx
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance status_csr_cg::OtpScramblingFsmErrIdx

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance status_csr_cg::OtpScramblingFsmErrIdx
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 0 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : status_csr_cg::OtpSecret0ErrIdx
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance status_csr_cg::OtpSecret0ErrIdx

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance status_csr_cg::OtpSecret0ErrIdx
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 0 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : status_csr_cg::OtpSecret1ErrIdx
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance status_csr_cg::OtpSecret1ErrIdx

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance status_csr_cg::OtpSecret1ErrIdx
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 0 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : status_csr_cg::OtpSecret2ErrIdx
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance status_csr_cg::OtpSecret2ErrIdx

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance status_csr_cg::OtpSecret2ErrIdx
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 0 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : status_csr_cg::OtpTimeoutErrIdx
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance status_csr_cg::OtpTimeoutErrIdx

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance status_csr_cg::OtpTimeoutErrIdx
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 0 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : status_csr_cg::OtpVendorTestErrIdx
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance status_csr_cg::OtpVendorTestErrIdx

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance status_csr_cg::OtpVendorTestErrIdx
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 0 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::PutFullData_mask_not_match_size
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::PutFullData_mask_not_match_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::PutFullData_mask_not_match_size
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::addr_not_align_mask
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::addr_not_align_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::addr_not_align_mask
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::addr_not_align_size
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::addr_not_align_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::addr_not_align_size
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::invalid_a_opcode
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::invalid_a_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::invalid_a_opcode
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::mask_not_in_enabled_lanes
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::mask_not_in_enabled_lanes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::mask_not_in_enabled_lanes
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::size_over_max
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::size_over_max

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::size_over_max
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::PutFullData_mask_not_match_size
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::PutFullData_mask_not_match_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::PutFullData_mask_not_match_size
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::addr_not_align_mask
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::addr_not_align_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::addr_not_align_mask
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::addr_not_align_size
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::addr_not_align_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::addr_not_align_size
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::invalid_a_opcode
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::invalid_a_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::invalid_a_opcode
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::mask_not_in_enabled_lanes
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::mask_not_in_enabled_lanes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::mask_not_in_enabled_lanes
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::size_over_max
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::size_over_max

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::size_over_max
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for cp_transitions

Uncovered bins
NAME   COUNT   AT LEAST   NUMBER   STATUS   
falling 0 1 1
rising 0 1 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2311438 1 T1 2164 T2 240 T3 737


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 20 1 T7 1 T271 1 T127 1
rising 43 1 T9 1 T7 1 T227 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 13317 1 T1 15 T2 2 T5 5
auto[1] 43 1 T9 1 T7 1 T227 1


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 35 1 T13 1 T126 4 T203 1
rising 72 1 T13 2 T94 1 T340 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 324 1 T96 1 T179 2 T13 3
auto[1] 358 1 T13 4 T93 6 T94 5


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 2864 1 T1 13 T2 1 T5 2
rising 2479 1 T1 12 T2 1 T5 2



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1348371 1 T1 1106 T2 101 T3 737
auto[1] 963067 1 T1 1058 T2 139 T5 1668


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 1524 1 T1 1 T2 1 T5 1
rising 1998 1 T1 2 T2 2 T5 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1557289 1 T1 935 T2 155 T3 737
auto[1] 754149 1 T1 1229 T2 85 T5 4


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 21070 1 T1 29 T2 1 T5 9
rising 21633 1 T1 30 T2 2 T5 9



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1832761 1 T1 1903 T2 154 T3 737
auto[1] 478677 1 T1 261 T2 86 T5 28


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 77733 1 T1 103 T2 5 T3 80
rising 77791 1 T1 103 T2 4 T3 81



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1149184 1 T1 794 T2 92 T3 610
auto[1] 1162254 1 T1 1370 T2 148 T3 127


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 82 1 T13 2 T12 1 T62 1
rising 279 1 T101 1 T63 1 T102 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 2179244 1 T1 2164 T2 240 T3 737
auto[1] 132194 1 T101 7 T63 93 T102 91


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 460 1 T2 1 T7 3 T13 3
rising 786 1 T2 2 T9 1 T6 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1945660 1 T1 2164 T2 155 T3 737
auto[1] 365778 1 T2 85 T9 513 T6 709


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 463 1 T2 1 T7 3 T13 3
rising 788 1 T2 2 T9 1 T6 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1945157 1 T1 2164 T2 155 T3 737
auto[1] 366281 1 T2 85 T9 513 T6 709


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 458 1 T2 1 T7 3 T13 3
rising 781 1 T2 2 T9 1 T6 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1936877 1 T1 2164 T2 155 T3 737
auto[1] 374561 1 T2 85 T9 567 T6 709


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 82 1 T13 2 T12 1 T62 1
rising 279 1 T101 1 T63 1 T102 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 2179244 1 T1 2164 T2 240 T3 737
auto[1] 132194 1 T101 7 T63 93 T102 91


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 460 1 T2 1 T7 3 T13 3
rising 786 1 T2 2 T9 1 T6 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1945390 1 T1 2164 T2 155 T3 737
auto[1] 366048 1 T2 85 T9 513 T6 709


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 1493 1 T2 1 T7 7 T33 4
rising 1934 1 T1 1 T2 2 T9 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1564082 1 T1 1696 T2 155 T3 737
auto[1] 747356 1 T1 468 T2 85 T9 536


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 1463 1 T2 1 T10 4 T15 1
rising 1935 1 T1 1 T2 2 T9 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1560584 1 T1 1733 T2 155 T3 737
auto[1] 750854 1 T1 431 T2 85 T9 532


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 1462 1 T1 1 T2 1 T10 2
rising 1924 1 T1 2 T2 2 T9 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1563121 1 T1 1664 T2 155 T3 737
auto[1] 748317 1 T1 500 T2 85 T9 513


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 82 1 T13 2 T12 1 T62 1
rising 279 1 T101 1 T63 1 T102 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 2179244 1 T1 2164 T2 240 T3 737
auto[1] 132194 1 T101 7 T63 93 T102 91


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 460 1 T2 1 T7 3 T13 3
rising 788 1 T2 2 T9 1 T6 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1945643 1 T1 2164 T2 155 T3 737
auto[1] 365795 1 T2 85 T9 513 T6 709


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 459 1 T2 1 T7 3 T13 3
rising 784 1 T2 2 T9 1 T6 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1946167 1 T1 2164 T2 155 T3 737
auto[1] 365271 1 T2 85 T9 513 T6 709


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 465 1 T2 1 T7 3 T13 3
rising 790 1 T2 2 T9 1 T6 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1944496 1 T1 2164 T2 155 T3 737
auto[1] 366942 1 T2 85 T9 513 T6 709


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 84 1 T50 3 T92 1 T35 2
rising 104 1 T50 3 T92 2 T35 3



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 2307472 1 T1 2164 T2 240 T3 737
auto[1] 3966 1 T50 112 T92 18 T35 56


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 1430 1 T1 1 T2 1 T5 1
rising 1889 1 T1 2 T2 2 T5 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1568337 1 T1 1497 T2 155 T3 737
auto[1] 743101 1 T1 667 T2 85 T5 236


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 3498306 1 T1 18202 T7 39719 T12 100231
rising 3498315 1 T1 18202 T7 39718 T12 100231



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 13506153 1 T1 69947 T7 153759 T12 387559
auto[1] 4758600 1 T1 25168 T7 53985 T12 135664


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 4150266 1 T1 21521 T7 47278 T12 119150
rising 4150281 1 T1 21521 T7 47279 T12 119151



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 11834399 1 T1 61768 T7 134122 T12 338426
auto[1] 6430354 1 T1 33347 T7 73622 T12 184797


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 4150266 1 T1 21521 T7 47278 T12 119150
rising 4150281 1 T1 21521 T7 47279 T12 119151



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 11834399 1 T1 61768 T7 134122 T12 338426
auto[1] 6430354 1 T1 33347 T7 73622 T12 184797


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 4202800 1 T1 21660 T7 48129 T12 120997
rising 4202790 1 T1 21660 T7 48129 T12 120996



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 11524886 1 T1 60498 T7 130530 T12 329928
auto[1] 6739867 1 T1 34617 T7 77214 T12 193295


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 3943465 1 T1 20543 T7 44826 T12 112970
rising 3943468 1 T1 20543 T7 44825 T12 112970



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 12475771 1 T1 64808 T7 142086 T12 357424
auto[1] 5788982 1 T1 30307 T7 65658 T12 165799


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 3528931 1 T1 18377 T7 40273 T12 101696
rising 3528935 1 T1 18377 T7 40274 T12 101697



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 13484661 1 T1 70225 T7 153073 T12 385193
auto[1] 4780092 1 T1 24890 T7 54671 T12 138030


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 1271614 1 T1 6536 T7 14163 T12 37284
rising 1271612 1 T1 6537 T7 14163 T12 37283



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 7460848 1 T1 38090 T7 84285 T12 226517
auto[1] 1598433 1 T1 8240 T7 17850 T12 46622


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 1845788 1 T1 9403 T7 20826 T12 55672
rising 1845785 1 T1 9402 T7 20826 T12 55672



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6463480 1 T1 33096 T7 72851 T12 194772
auto[1] 2595801 1 T1 13234 T7 29284 T12 78367


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 1845788 1 T1 9403 T7 20826 T12 55672
rising 1845785 1 T1 9402 T7 20826 T12 55672



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6463480 1 T1 33096 T7 72851 T12 194772
auto[1] 2595801 1 T1 13234 T7 29284 T12 78367


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 1915041 1 T1 9790 T7 21575 T12 58013
rising 1915062 1 T1 9790 T7 21575 T12 58013



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6204756 1 T1 31797 T7 69938 T12 185830
auto[1] 2854525 1 T1 14533 T7 32197 T12 87309


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 1602899 1 T1 8293 T7 18157 T12 48332
rising 1602884 1 T1 8293 T7 18157 T12 48332



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6928768 1 T1 35282 T7 77903 T12 208980
auto[1] 2130513 1 T1 11048 T7 24232 T12 64159


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 1527277 1 T1 7877 T7 17177 T12 46585
rising 1527269 1 T1 7876 T7 17177 T12 46585



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 7109143 1 T1 36114 T7 80137 T12 213415
auto[1] 1950138 1 T1 10216 T7 21998 T12 59724