Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.19	94.16	96.15	97.02		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.19	94.16	96.15	97.02		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T64,T40,T137

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T4,T8
1	Covered	T138,T50,T139

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T18,T19,T20

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T70,T72,T140
1	Covered	T70,T72,T140

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T8

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T3,T4,T8

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T3,T4,T8
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T3,T4,T8
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T10,T24

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T10,T24

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T4
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T3,T4
ReadWaitSt	252	Covered	T3,T4,T8
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T4,T8
IdleSt->ReadSt	236	Covered	T1,T3,T4
InitSt->ErrorSt	315	Covered	T147,T148,T69
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T3,T97,T107
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T9,T10
ReadSt->ReadWaitSt	252	Covered	T3,T4,T8
ReadWaitSt->ErrorSt	276	Covered	T149,T189,T190
ReadWaitSt->IdleSt	270	Covered	T3,T4,T8
ResetSt->ErrorSt	315	Covered	T70,T71,T72
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T9,T10
CheckFailError	317	Covered	T70,T72,T140
FsmStateError	289	Covered	T2,T3,T4
MacroEccCorrError	221	Covered	T64,T138,T50
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T9,T7,T12
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T10,T15
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T70,T72,T140
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T4
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T64,T138,T40
MacroEccCorrError->NoError	235	Covered	T138,T50,T139
NoError->AccessError	256	Covered	T1,T9,T10
NoError->CheckFailError	317	Covered	T70,T72,T140
NoError->FsmStateError	289	Covered	T2,T3,T4
NoError->MacroEccCorrError	221	Covered	T64,T138,T50

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T8

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T8

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T24
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T64,T40,T137
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T107,T167,T191
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T3,T4,T8
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T24,T34,T13
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T9,T10
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T138,T50,T139
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T3,T4,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T149,T189,T190
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T3,T4,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T18,T19,T20
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T9,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T9,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T70,T72,T140
1	0	Covered	T70,T72,T140
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	446856597	446009146	0	0
DigestKnown_A	446856597	446009146	0	0
DigestOffsetMustBeRepresentable_A	1143	1143	0	0
EccErrorState_A	446856597	9192	0	0
ErrorKnown_A	446856597	446009146	0	0
FsmStateKnown_A	446856597	446009146	0	0
InitDoneKnown_A	446856597	446009146	0	0
InitReadLocksPartition_A	446856597	75827513	0	0
InitWriteLocksPartition_A	446856597	75827513	0	0
OffsetMustBeBlockAligned_A	1143	1143	0	0
OtpAddrKnown_A	446856597	446009146	0	0
OtpCmdKnown_A	446856597	446009146	0	0
OtpErrorState_A	446856597	45	0	0
OtpReqKnown_A	446856597	446009146	0	0
OtpSizeKnown_A	446856597	446009146	0	0
OtpWdataKnown_A	446856597	446009146	0	0
ReadLockPropagation_A	446856597	187311970	0	0
SizeMustBeBlockAligned_A	1143	1143	0	0
TlulGntKnown_A	446856597	446009146	0	0
TlulRdataKnown_A	446856597	446009146	0	0
TlulReadOnReadLock_A	446856597	7631	0	0
TlulRerrorKnown_A	446856597	446009146	0	0
TlulRvalidKnown_A	446856597	446009146	0	0
WriteLockPropagation_A	446856597	3584399	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	446856597	31567964	0	0
u_state_regs_A	446856597	446009146	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	446009146	0	0
T1	210721	210711	0	0
T2	40924	40436	0	0
T3	9081	8905	0	0
T4	16049	15818	0	0
T5	38663	37886	0	0
T6	32483	32265	0	0
T8	10823	10585	0	0
T9	106712	106487	0	0
T10	54564	53814	0	0
T11	17872	17688	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	446009146	0	0
T1	210721	210711	0	0
T2	40924	40436	0	0
T3	9081	8905	0	0
T4	16049	15818	0	0
T5	38663	37886	0	0
T6	32483	32265	0	0
T8	10823	10585	0	0
T9	106712	106487	0	0
T10	54564	53814	0	0
T11	17872	17688	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	9192	0	0
T30	18935	0	0	0
T70	14677	2906	0	0
T72	0	2549	0	0
T140	0	3737	0	0
T150	9404	0	0	0
T151	12839	0	0	0
T152	15587	0	0	0
T153	4435	0	0	0
T154	10808	0	0	0
T155	13913	0	0	0
T156	25244	0	0	0
T157	67468	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	446009146	0	0
T1	210721	210711	0	0
T2	40924	40436	0	0
T3	9081	8905	0	0
T4	16049	15818	0	0
T5	38663	37886	0	0
T6	32483	32265	0	0
T8	10823	10585	0	0
T9	106712	106487	0	0
T10	54564	53814	0	0
T11	17872	17688	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	446009146	0	0
T1	210721	210711	0	0
T2	40924	40436	0	0
T3	9081	8905	0	0
T4	16049	15818	0	0
T5	38663	37886	0	0
T6	32483	32265	0	0
T8	10823	10585	0	0
T9	106712	106487	0	0
T10	54564	53814	0	0
T11	17872	17688	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	446009146	0	0
T1	210721	210711	0	0
T2	40924	40436	0	0
T3	9081	8905	0	0
T4	16049	15818	0	0
T5	38663	37886	0	0
T6	32483	32265	0	0
T8	10823	10585	0	0
T9	106712	106487	0	0
T10	54564	53814	0	0
T11	17872	17688	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	75827513	0	0
T1	210721	735	0	0
T2	40924	16656	0	0
T3	9081	3336	0	0
T4	16049	5729	0	0
T5	38663	864	0	0
T6	32483	25036	0	0
T8	10823	3504	0	0
T9	106712	92851	0	0
T10	54564	1184	0	0
T11	17872	183	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	75827513	0	0
T1	210721	735	0	0
T2	40924	16656	0	0
T3	9081	3336	0	0
T4	16049	5729	0	0
T5	38663	864	0	0
T6	32483	25036	0	0
T8	10823	3504	0	0
T9	106712	92851	0	0
T10	54564	1184	0	0
T11	17872	183	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	446009146	0	0
T1	210721	210711	0	0
T2	40924	40436	0	0
T3	9081	8905	0	0
T4	16049	15818	0	0
T5	38663	37886	0	0
T6	32483	32265	0	0
T8	10823	10585	0	0
T9	106712	106487	0	0
T10	54564	53814	0	0
T11	17872	17688	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	446009146	0	0
T1	210721	210711	0	0
T2	40924	40436	0	0
T3	9081	8905	0	0
T4	16049	15818	0	0
T5	38663	37886	0	0
T6	32483	32265	0	0
T8	10823	10585	0	0
T9	106712	106487	0	0
T10	54564	53814	0	0
T11	17872	17688	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	45	0	0
T13	543072	0	0	0
T33	112154	0	0	0
T34	41882	0	0	0
T103	57312	0	0	0
T107	13414	1	0	0
T143	8874	0	0	0
T149	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T167	0	1	0	0
T182	9563	0	0	0
T183	11431	0	0	0
T184	63664	0	0	0
T185	16541	0	0	0
T191	0	1	0	0
T192	0	1	0	0
T193	0	1	0	0
T194	0	1	0	0
T195	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	446009146	0	0
T1	210721	210711	0	0
T2	40924	40436	0	0
T3	9081	8905	0	0
T4	16049	15818	0	0
T5	38663	37886	0	0
T6	32483	32265	0	0
T8	10823	10585	0	0
T9	106712	106487	0	0
T10	54564	53814	0	0
T11	17872	17688	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	446009146	0	0
T1	210721	210711	0	0
T2	40924	40436	0	0
T3	9081	8905	0	0
T4	16049	15818	0	0
T5	38663	37886	0	0
T6	32483	32265	0	0
T8	10823	10585	0	0
T9	106712	106487	0	0
T10	54564	53814	0	0
T11	17872	17688	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	446009146	0	0
T1	210721	210711	0	0
T2	40924	40436	0	0
T3	9081	8905	0	0
T4	16049	15818	0	0
T5	38663	37886	0	0
T6	32483	32265	0	0
T8	10823	10585	0	0
T9	106712	106487	0	0
T10	54564	53814	0	0
T11	17872	17688	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	187311970	0	0
T1	210721	692858	0	0
T2	40924	0	0	0
T3	9081	0	0	0
T4	16049	0	0	0
T5	38663	3594	0	0
T6	32483	0	0	0
T7	0	147028	0	0
T8	10823	0	0	0
T9	106712	95625	0	0
T10	54564	8529	0	0
T11	17872	0	0	0
T15	0	877	0	0
T33	0	5615	0	0
T34	0	1656	0	0
T63	0	2351	0	0
T179	0	13880	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	446009146	0	0
T1	210721	210711	0	0
T2	40924	40436	0	0
T3	9081	8905	0	0
T4	16049	15818	0	0
T5	38663	37886	0	0
T6	32483	32265	0	0
T8	10823	10585	0	0
T9	106712	106487	0	0
T10	54564	53814	0	0
T11	17872	17688	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	446009146	0	0
T1	210721	210711	0	0
T2	40924	40436	0	0
T3	9081	8905	0	0
T4	16049	15818	0	0
T5	38663	37886	0	0
T6	32483	32265	0	0
T8	10823	10585	0	0
T9	106712	106487	0	0
T10	54564	53814	0	0
T11	17872	17688	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	7631	0	0
T1	210721	5	0	0
T2	40924	1	0	0
T3	9081	0	0	0
T4	16049	0	0	0
T5	38663	0	0	0
T6	32483	16	0	0
T8	10823	0	0	0
T9	106712	19	0	0
T10	54564	8	0	0
T11	17872	0	0	0
T15	0	2	0	0
T63	0	2	0	0
T96	0	1	0	0
T98	0	6	0	0
T102	0	1	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	446009146	0	0
T1	210721	210711	0	0
T2	40924	40436	0	0
T3	9081	8905	0	0
T4	16049	15818	0	0
T5	38663	37886	0	0
T6	32483	32265	0	0
T8	10823	10585	0	0
T9	106712	106487	0	0
T10	54564	53814	0	0
T11	17872	17688	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	446009146	0	0
T1	210721	210711	0	0
T2	40924	40436	0	0
T3	9081	8905	0	0
T4	16049	15818	0	0
T5	38663	37886	0	0
T6	32483	32265	0	0
T8	10823	10585	0	0
T9	106712	106487	0	0
T10	54564	53814	0	0
T11	17872	17688	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	3584399	0	0
T5	38663	2942	0	0
T6	32483	0	0	0
T8	10823	0	0	0
T9	106712	0	0	0
T10	54564	0	0	0
T11	17872	0	0	0
T13	0	36296	0	0
T15	0	2715	0	0
T24	73599	0	0	0
T33	0	4238	0	0
T50	0	5480	0	0
T62	0	9050	0	0
T87	0	5757	0	0
T96	167263	0	0	0
T97	11116	0	0	0
T98	37419	0	0	0
T99	0	1984	0	0
T104	0	4387	0	0
T130	0	11315	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	31567964	0	0
T5	38663	28006	0	0
T6	32483	0	0	0
T8	10823	0	0	0
T9	106712	0	0	0
T10	54564	44722	0	0
T11	17872	0	0	0
T13	0	298956	0	0
T15	0	43950	0	0
T24	73599	40525	0	0
T33	0	61380	0	0
T34	0	22270	0	0
T96	167263	0	0	0
T97	11116	0	0	0
T98	37419	0	0	0
T103	0	2534	0	0
T107	0	2364	0	0
T179	0	4908	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	446009146	0	0
T1	210721	210711	0	0
T2	40924	40436	0	0
T3	9081	8905	0	0
T4	16049	15818	0	0
T5	38663	37886	0	0
T6	32483	32265	0	0
T8	10823	10585	0	0
T9	106712	106487	0	0
T10	54564	53814	0	0
T11	17872	17688	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T64,T40

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T50,T92,T146

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T18,T19,T20

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T70,T141
1	Covered	T70,T141

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T8

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T10,T65

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T10,T65

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T4
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T3,T4
ReadWaitSt	252	Covered	T1,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T8,T9
IdleSt->ReadSt	236	Covered	T1,T3,T4
InitSt->ErrorSt	315	Covered	T3,T97,T143
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T4,T65,T107
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T10,T7
ReadSt->ReadWaitSt	252	Covered	T1,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T146,T166,T188
ReadWaitSt->IdleSt	270	Covered	T1,T3,T4
ResetSt->ErrorSt	315	Covered	T70,T71,T72
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T10,T7
CheckFailError	317	Covered	T70,T141
FsmStateError	289	Covered	T2,T3,T8
MacroEccCorrError	221	Covered	T8,T64,T50
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T7,T103,T178
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T10,T7
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T70,T141
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T8
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T8,T64,T40
MacroEccCorrError->NoError	235	Covered	T50,T92,T146
NoError->AccessError	256	Covered	T1,T10,T7
NoError->CheckFailError	317	Covered	T70,T141
NoError->FsmStateError	289	Covered	T2,T3,T9
NoError->MacroEccCorrError	221	Covered	T8,T64,T50

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T10,T65
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T8,T64,T40
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T4,T65,T182
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T34,T93,T62
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T10,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T50,T92,T146
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T146,T166,T188
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T18,T19,T20
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T9,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T9,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T70,T141
1	0	Covered	T70,T141
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	446856597	446009146	0	0
DigestKnown_A	446856597	446009146	0	0
DigestOffsetMustBeRepresentable_A	1143	1143	0	0
EccErrorState_A	446856597	5340	0	0
ErrorKnown_A	446856597	446009146	0	0
FsmStateKnown_A	446856597	446009146	0	0
InitDoneKnown_A	446856597	446009146	0	0
InitReadLocksPartition_A	446856597	76004239	0	0
InitWriteLocksPartition_A	446856597	76004239	0	0
OffsetMustBeBlockAligned_A	1143	1143	0	0
OtpAddrKnown_A	446856597	446009146	0	0
OtpCmdKnown_A	446856597	446009146	0	0
OtpErrorState_A	446856597	46	0	0
OtpReqKnown_A	446856597	446009146	0	0
OtpSizeKnown_A	446856597	446009146	0	0
OtpWdataKnown_A	446856597	446009146	0	0
ReadLockPropagation_A	446856597	194984160	0	0
SizeMustBeBlockAligned_A	1143	1143	0	0
TlulGntKnown_A	446856597	446009146	0	0
TlulRdataKnown_A	446856597	446009146	0	0
TlulReadOnReadLock_A	446856597	7252	0	0
TlulRerrorKnown_A	446856597	446009146	0	0
TlulRvalidKnown_A	446856597	446009146	0	0
WriteLockPropagation_A	446856597	1712623	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	446856597	12211701	0	0
u_state_regs_A	446856597	446009146	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	446009146	0	0
T1	210721	210711	0	0
T2	40924	40436	0	0
T3	9081	8905	0	0
T4	16049	15818	0	0
T5	38663	37886	0	0
T6	32483	32265	0	0
T8	10823	10585	0	0
T9	106712	106487	0	0
T10	54564	53814	0	0
T11	17872	17688	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	446009146	0	0
T1	210721	210711	0	0
T2	40924	40436	0	0
T3	9081	8905	0	0
T4	16049	15818	0	0
T5	38663	37886	0	0
T6	32483	32265	0	0
T8	10823	10585	0	0
T9	106712	106487	0	0
T10	54564	53814	0	0
T11	17872	17688	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	5340	0	0
T30	18935	0	0	0
T70	14677	2906	0	0
T141	0	2434	0	0
T150	9404	0	0	0
T151	12839	0	0	0
T152	15587	0	0	0
T153	4435	0	0	0
T154	10808	0	0	0
T155	13913	0	0	0
T156	25244	0	0	0
T157	67468	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	446009146	0	0
T1	210721	210711	0	0
T2	40924	40436	0	0
T3	9081	8905	0	0
T4	16049	15818	0	0
T5	38663	37886	0	0
T6	32483	32265	0	0
T8	10823	10585	0	0
T9	106712	106487	0	0
T10	54564	53814	0	0
T11	17872	17688	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	446009146	0	0
T1	210721	210711	0	0
T2	40924	40436	0	0
T3	9081	8905	0	0
T4	16049	15818	0	0
T5	38663	37886	0	0
T6	32483	32265	0	0
T8	10823	10585	0	0
T9	106712	106487	0	0
T10	54564	53814	0	0
T11	17872	17688	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	446009146	0	0
T1	210721	210711	0	0
T2	40924	40436	0	0
T3	9081	8905	0	0
T4	16049	15818	0	0
T5	38663	37886	0	0
T6	32483	32265	0	0
T8	10823	10585	0	0
T9	106712	106487	0	0
T10	54564	53814	0	0
T11	17872	17688	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	76004239	0	0
T1	210721	837	0	0
T2	40924	16758	0	0
T3	9081	3353	0	0
T4	16049	5770	0	0
T5	38663	1000	0	0
T6	32483	25087	0	0
T8	10823	3538	0	0
T9	106712	92902	0	0
T10	54564	1303	0	0
T11	17872	217	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	76004239	0	0
T1	210721	837	0	0
T2	40924	16758	0	0
T3	9081	3353	0	0
T4	16049	5770	0	0
T5	38663	1000	0	0
T6	32483	25087	0	0
T8	10823	3538	0	0
T9	106712	92902	0	0
T10	54564	1303	0	0
T11	17872	217	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	446009146	0	0
T1	210721	210711	0	0
T2	40924	40436	0	0
T3	9081	8905	0	0
T4	16049	15818	0	0
T5	38663	37886	0	0
T6	32483	32265	0	0
T8	10823	10585	0	0
T9	106712	106487	0	0
T10	54564	53814	0	0
T11	17872	17688	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	446009146	0	0
T1	210721	210711	0	0
T2	40924	40436	0	0
T3	9081	8905	0	0
T4	16049	15818	0	0
T5	38663	37886	0	0
T6	32483	32265	0	0
T8	10823	10585	0	0
T9	106712	106487	0	0
T10	54564	53814	0	0
T11	17872	17688	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	46	0	0
T4	16049	1	0	0
T5	38663	0	0	0
T6	32483	0	0	0
T8	10823	0	0	0
T9	106712	0	0	0
T10	54564	0	0	0
T11	17872	0	0	0
T24	73599	0	0	0
T65	0	1	0	0
T96	167263	0	0	0
T97	11116	0	0	0
T137	0	1	0	0
T146	0	1	0	0
T150	0	1	0	0
T182	0	1	0	0
T196	0	1	0	0
T197	0	1	0	0
T198	0	1	0	0
T199	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	446009146	0	0
T1	210721	210711	0	0
T2	40924	40436	0	0
T3	9081	8905	0	0
T4	16049	15818	0	0
T5	38663	37886	0	0
T6	32483	32265	0	0
T8	10823	10585	0	0
T9	106712	106487	0	0
T10	54564	53814	0	0
T11	17872	17688	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	446009146	0	0
T1	210721	210711	0	0
T2	40924	40436	0	0
T3	9081	8905	0	0
T4	16049	15818	0	0
T5	38663	37886	0	0
T6	32483	32265	0	0
T8	10823	10585	0	0
T9	106712	106487	0	0
T10	54564	53814	0	0
T11	17872	17688	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	446009146	0	0
T1	210721	210711	0	0
T2	40924	40436	0	0
T3	9081	8905	0	0
T4	16049	15818	0	0
T5	38663	37886	0	0
T6	32483	32265	0	0
T8	10823	10585	0	0
T9	106712	106487	0	0
T10	54564	53814	0	0
T11	17872	17688	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	194984160	0	0
T1	210721	692839	0	0
T2	40924	8313	0	0
T3	9081	0	0	0
T4	16049	0	0	0
T5	38663	4311	0	0
T6	32483	25202	0	0
T7	0	149302	0	0
T8	10823	0	0	0
T9	106712	0	0	0
T10	54564	8975	0	0
T11	17872	0	0	0
T15	0	2578	0	0
T24	0	124	0	0
T33	0	7053	0	0
T179	0	13876	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	446009146	0	0
T1	210721	210711	0	0
T2	40924	40436	0	0
T3	9081	8905	0	0
T4	16049	15818	0	0
T5	38663	37886	0	0
T6	32483	32265	0	0
T8	10823	10585	0	0
T9	106712	106487	0	0
T10	54564	53814	0	0
T11	17872	17688	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	446009146	0	0
T1	210721	210711	0	0
T2	40924	40436	0	0
T3	9081	8905	0	0
T4	16049	15818	0	0
T5	38663	37886	0	0
T6	32483	32265	0	0
T8	10823	10585	0	0
T9	106712	106487	0	0
T10	54564	53814	0	0
T11	17872	17688	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	7252	0	0
T1	210721	6	0	0
T2	40924	2	0	0
T3	9081	0	0	0
T4	16049	0	0	0
T5	38663	0	0	0
T6	32483	30	0	0
T7	0	78	0	0
T8	10823	0	0	0
T9	106712	18	0	0
T10	54564	4	0	0
T11	17872	0	0	0
T63	0	6	0	0
T96	0	1	0	0
T98	0	7	0	0
T102	0	3	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	446009146	0	0
T1	210721	210711	0	0
T2	40924	40436	0	0
T3	9081	8905	0	0
T4	16049	15818	0	0
T5	38663	37886	0	0
T6	32483	32265	0	0
T8	10823	10585	0	0
T9	106712	106487	0	0
T10	54564	53814	0	0
T11	17872	17688	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	446009146	0	0
T1	210721	210711	0	0
T2	40924	40436	0	0
T3	9081	8905	0	0
T4	16049	15818	0	0
T5	38663	37886	0	0
T6	32483	32265	0	0
T8	10823	10585	0	0
T9	106712	106487	0	0
T10	54564	53814	0	0
T11	17872	17688	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	1712623	0	0
T13	543072	0	0	0
T33	112154	5517	0	0
T34	41882	596	0	0
T50	0	7969	0	0
T69	0	5011	0	0
T87	0	5757	0	0
T103	57312	0	0	0
T113	0	11259	0	0
T126	0	52205	0	0
T143	8874	0	0	0
T147	16340	0	0	0
T157	0	9326	0	0
T182	9563	0	0	0
T183	11431	0	0	0
T184	63664	0	0	0
T185	16541	0	0	0
T200	0	5462	0	0
T201	0	30964	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	12211701	0	0
T4	16049	3467	0	0
T5	38663	0	0	0
T6	32483	0	0	0
T8	10823	0	0	0
T9	106712	0	0	0
T10	54564	44620	0	0
T11	17872	0	0	0
T13	0	84663	0	0
T24	73599	0	0	0
T33	0	51627	0	0
T34	0	29940	0	0
T50	0	97848	0	0
T65	0	3884	0	0
T96	167263	0	0	0
T97	11116	0	0	0
T103	0	2517	0	0
T179	0	4874	0	0
T182	0	2519	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446856597	446009146	0	0
T1	210721	210711	0	0
T2	40924	40436	0	0
T3	9081	8905	0	0
T4	16049	15818	0	0
T5	38663	37886	0	0
T6	32483	32265	0	0
T8	10823	10585	0	0
T9	106712	106487	0	0
T10	54564	53814	0	0
T11	17872	17688	0	0