Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 7477102 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 7431513 1 T1 575 T2 174 T3 153



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 8590068 1 T1 1444 T2 1387 T3 275
values[0x0] 2396236 1 T1 101 T2 24 T3 82
values[0x1] 3922311 1 T1 80 T2 29 T3 104



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 4824673 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 10083942 1 T1 838 T2 541 T3 236



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 58564 1 T4 10 T10 6 T11 7
valid_sources[0x01] 52377 1 T4 3 T10 2 T11 14
valid_sources[0x02] 60781 1 T10 1 T11 6 T12 94
valid_sources[0x03] 54240 1 T4 2 T10 1 T11 2
valid_sources[0x04] 62818 1 T3 3 T4 2 T10 1
valid_sources[0x05] 64986 1 T4 1 T10 7 T11 5
valid_sources[0x06] 56594 1 T10 4 T11 5 T12 112
valid_sources[0x07] 58474 1 T3 6 T4 1 T6 1
valid_sources[0x08] 58125 1 T4 3 T11 8 T12 131
valid_sources[0x09] 60604 1 T4 7 T10 2 T11 3
valid_sources[0x0a] 51497 1 T3 2 T4 1 T11 5
valid_sources[0x0b] 57237 1 T3 10 T10 3 T11 7
valid_sources[0x0c] 64776 1 T4 16 T10 2 T11 10
valid_sources[0x0d] 66735 1 T4 4 T10 1 T11 8
valid_sources[0x0e] 123001 1 T4 3 T10 1 T11 7
valid_sources[0x0f] 51250 1 T10 1 T11 9 T12 120
valid_sources[0x10] 55874 1 T4 3 T10 1 T11 15
valid_sources[0x11] 62657 1 T4 1 T6 1 T10 2
valid_sources[0x12] 58786 1 T4 4 T10 3 T11 2
valid_sources[0x13] 50561 1 T4 1 T10 3 T11 9
valid_sources[0x14] 51598 1 T4 3 T10 7 T11 10
valid_sources[0x15] 54800 1 T4 1 T11 2 T12 112
valid_sources[0x16] 65468 1 T4 5 T10 2 T11 6
valid_sources[0x17] 59500 1 T4 4 T11 14 T12 102
valid_sources[0x18] 65059 1 T4 4 T10 3 T11 10
valid_sources[0x19] 60675 1 T4 1 T10 5 T11 6
valid_sources[0x1a] 55385 1 T4 7 T10 2 T11 3
valid_sources[0x1b] 57210 1 T3 11 T10 2 T11 15
valid_sources[0x1c] 62585 1 T4 3 T6 1 T10 3
valid_sources[0x1d] 52275 1 T4 3 T6 3 T10 3
valid_sources[0x1e] 57225 1 T4 4 T11 6 T12 104
valid_sources[0x1f] 54779 1 T4 10 T10 1 T11 9
valid_sources[0x20] 68648 1 T4 3 T10 3 T11 10
valid_sources[0x21] 61378 1 T4 3 T10 1 T11 11
valid_sources[0x22] 51633 1 T4 1 T10 7 T11 14
valid_sources[0x23] 51717 1 T4 7 T10 4 T11 12
valid_sources[0x24] 53048 1 T4 2 T10 2 T11 8
valid_sources[0x25] 56260 1 T4 8 T11 6 T12 108
valid_sources[0x26] 53028 1 T4 2 T10 5 T11 3
valid_sources[0x27] 56590 1 T4 6 T6 2 T10 6
valid_sources[0x28] 56638 1 T4 8 T11 4 T12 108
valid_sources[0x29] 52484 1 T4 10 T6 2 T10 1
valid_sources[0x2a] 51519 1 T4 1 T10 5 T11 7
valid_sources[0x2b] 52611 1 T3 1 T4 3 T10 1
valid_sources[0x2c] 51750 1 T10 3 T11 10 T12 126
valid_sources[0x2d] 62030 1 T3 6 T4 7 T10 5
valid_sources[0x2e] 51673 1 T11 4 T12 92 T13 4
valid_sources[0x2f] 51688 1 T4 12 T10 1 T11 17
valid_sources[0x30] 66294 1 T3 14 T4 4 T10 1
valid_sources[0x31] 56768 1 T4 2 T10 1 T11 6
valid_sources[0x32] 51195 1 T4 3 T10 4 T11 8
valid_sources[0x33] 54831 1 T10 4 T11 5 T12 116
valid_sources[0x34] 63907 1 T6 8 T10 5 T11 6
valid_sources[0x35] 51367 1 T10 1 T11 14 T12 92
valid_sources[0x36] 57150 1 T2 1440 T4 3 T10 2
valid_sources[0x37] 67831 1 T4 2 T10 1 T11 7
valid_sources[0x38] 52618 1 T3 11 T4 2 T10 4
valid_sources[0x39] 104517 1 T4 3 T10 6 T11 7
valid_sources[0x3a] 55690 1 T4 7 T11 6 T12 109
valid_sources[0x3b] 50898 1 T4 2 T10 7 T11 10
valid_sources[0x3c] 52252 1 T4 5 T6 2 T11 12
valid_sources[0x3d] 53477 1 T4 1 T6 2 T10 3
valid_sources[0x3e] 50579 1 T3 9 T4 5 T10 5
valid_sources[0x3f] 53293 1 T4 2 T10 4 T11 8
valid_sources[0x40] 54039 1 T4 3 T10 1 T11 10
valid_sources[0x41] 51608 1 T4 1 T10 7 T11 12
valid_sources[0x42] 78257 1 T4 6 T10 3 T11 13
valid_sources[0x43] 53081 1 T3 6 T4 3 T10 2
valid_sources[0x44] 81968 1 T4 3 T10 3 T11 13
valid_sources[0x45] 53560 1 T4 5 T6 2 T10 1
valid_sources[0x46] 52281 1 T4 2 T11 14 T12 112
valid_sources[0x47] 63179 1 T4 3 T10 3 T11 8
valid_sources[0x48] 53284 1 T4 1 T10 5 T11 7
valid_sources[0x49] 52010 1 T3 12 T4 5 T6 1
valid_sources[0x4a] 55600 1 T3 10 T4 5 T10 2
valid_sources[0x4b] 52902 1 T1 1625 T4 2 T10 1
valid_sources[0x4c] 55077 1 T10 3 T11 7 T12 112
valid_sources[0x4d] 52544 1 T10 1 T11 11 T12 112
valid_sources[0x4e] 54561 1 T3 4 T4 3 T10 1
valid_sources[0x4f] 52599 1 T4 1 T10 1 T11 22
valid_sources[0x50] 53159 1 T4 1 T6 1 T10 2
valid_sources[0x51] 58865 1 T4 2 T10 1 T11 6
valid_sources[0x52] 53291 1 T3 28 T6 2 T10 5
valid_sources[0x53] 56448 1 T4 5 T11 9 T12 114
valid_sources[0x54] 54043 1 T10 1 T11 6 T12 90
valid_sources[0x55] 53932 1 T4 1 T11 5 T12 96
valid_sources[0x56] 60269 1 T4 4 T10 5 T11 5
valid_sources[0x57] 51323 1 T3 3 T10 2 T11 6
valid_sources[0x58] 52787 1 T4 2 T10 1 T11 2
valid_sources[0x59] 79604 1 T4 1 T10 1 T11 7
valid_sources[0x5a] 57699 1 T10 3 T11 18 T12 113
valid_sources[0x5b] 54737 1 T4 6 T10 2 T11 5
valid_sources[0x5c] 58194 1 T3 1 T4 3 T10 2
valid_sources[0x5d] 52395 1 T3 11 T4 4 T10 1
valid_sources[0x5e] 52176 1 T6 2 T10 2 T11 9
valid_sources[0x5f] 61236 1 T4 3 T10 2 T11 4
valid_sources[0x60] 55341 1 T4 2 T10 5 T11 3
valid_sources[0x61] 69953 1 T4 1 T11 3 T12 99
valid_sources[0x62] 54196 1 T10 3 T11 4 T12 119
valid_sources[0x63] 53935 1 T4 1 T6 2 T11 1
valid_sources[0x64] 62269 1 T4 1 T10 1 T11 7
valid_sources[0x65] 60874 1 T4 2 T10 2 T11 6
valid_sources[0x66] 49625 1 T3 1 T4 5 T11 4
valid_sources[0x67] 53153 1 T3 11 T4 3 T10 1
valid_sources[0x68] 53184 1 T3 6 T11 7 T12 111
valid_sources[0x69] 59171 1 T4 5 T10 4 T12 107
valid_sources[0x6a] 74492 1 T4 11 T6 1 T10 3
valid_sources[0x6b] 54658 1 T4 1 T10 3 T11 9
valid_sources[0x6c] 54469 1 T4 3 T10 2 T11 7
valid_sources[0x6d] 52111 1 T10 4 T11 9 T12 104
valid_sources[0x6e] 58252 1 T4 8 T10 2 T11 7
valid_sources[0x6f] 72425 1 T3 8 T4 1 T6 4
valid_sources[0x70] 51385 1 T4 7 T10 4 T11 2
valid_sources[0x71] 53859 1 T3 42 T4 5 T11 13
valid_sources[0x72] 53586 1 T4 2 T10 9 T11 4
valid_sources[0x73] 58171 1 T11 8 T12 97 T13 39
valid_sources[0x74] 66861 1 T3 2 T6 1 T11 11
valid_sources[0x75] 53306 1 T4 2 T6 3 T10 2
valid_sources[0x76] 60833 1 T3 2 T4 3 T11 9
valid_sources[0x77] 56659 1 T3 18 T10 2 T11 1
valid_sources[0x78] 84258 1 T6 2 T10 3 T11 8
valid_sources[0x79] 57770 1 T10 2 T11 5 T12 108
valid_sources[0x7a] 53934 1 T4 1 T10 5 T11 7
valid_sources[0x7b] 55960 1 T6 3 T10 4 T11 9
valid_sources[0x7c] 62797 1 T3 3 T4 3 T11 4
valid_sources[0x7d] 61323 1 T4 5 T10 2 T11 9
valid_sources[0x7e] 69266 1 T10 2 T11 4 T12 109
valid_sources[0x7f] 57515 1 T4 4 T10 10 T11 4
valid_sources[0x80] 50193 1 T4 1 T10 4 T11 4



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 3508312 1 T1 496 T2 149 T3 79
values[0x0] all_enables biggest_size 1998819 1 T1 48 T2 13 T3 44
values[0x1] all_enables biggest_size 1924382 1 T1 31 T2 12 T3 30


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 261448 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 9418954 1 T1 20 T2 20 T5 140



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 2409312 1 T1 10 T2 10 T5 70
values[0x0] 3530777 1 T1 5 T2 7 T5 34
values[0x1] 3740313 1 T1 5 T2 3 T5 36



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 94464 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 9585938 1 T1 20 T2 20 T5 140



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 38201 1 T11 1 T12 11 T8 294
valid_sources[0x01] 38008 1 T5 4 T12 4 T106 1
valid_sources[0x02] 36823 1 T12 25 T7 11 T199 1
valid_sources[0x03] 37472 1 T5 1 T8 330 T9 139
valid_sources[0x04] 37840 1 T11 2 T12 23 T7 20
valid_sources[0x05] 38762 1 T5 1 T7 9 T107 1
valid_sources[0x06] 38000 1 T12 7 T8 299 T38 1
valid_sources[0x07] 37766 1 T5 1 T8 309 T91 2
valid_sources[0x08] 36652 1 T11 1 T8 304 T91 2
valid_sources[0x09] 38718 1 T12 3 T199 2 T8 299
valid_sources[0x0a] 37928 1 T199 1 T8 294 T9 182
valid_sources[0x0b] 37922 1 T12 12 T108 1 T8 310
valid_sources[0x0c] 37531 1 T11 1 T12 1 T7 1
valid_sources[0x0d] 36660 1 T12 19 T107 1 T199 1
valid_sources[0x0e] 38838 1 T11 1 T12 7 T7 21
valid_sources[0x0f] 39590 1 T12 9 T7 4 T106 1
valid_sources[0x10] 37722 1 T12 1 T7 25 T8 303
valid_sources[0x11] 36947 1 T5 1 T199 2 T8 287
valid_sources[0x12] 36706 1 T199 4 T8 326 T38 1
valid_sources[0x13] 38433 1 T5 1 T12 20 T8 319
valid_sources[0x14] 39203 1 T12 17 T198 3 T199 3
valid_sources[0x15] 37841 1 T106 3 T8 314 T38 1
valid_sources[0x16] 38062 1 T11 3 T7 5 T102 1
valid_sources[0x17] 37406 1 T7 30 T8 313 T9 157
valid_sources[0x18] 37364 1 T11 1 T12 1 T7 19
valid_sources[0x19] 38757 1 T11 1 T12 8 T108 1
valid_sources[0x1a] 36772 1 T12 4 T8 295 T38 1
valid_sources[0x1b] 37080 1 T106 1 T198 4 T199 1
valid_sources[0x1c] 37191 1 T5 1 T12 11 T106 1
valid_sources[0x1d] 38772 1 T12 7 T7 3 T106 2
valid_sources[0x1e] 37661 1 T5 4 T12 8 T106 1
valid_sources[0x1f] 37113 1 T5 1 T12 3 T199 1
valid_sources[0x20] 37119 1 T12 3 T106 1 T199 1
valid_sources[0x21] 38006 1 T199 3 T8 344 T91 1
valid_sources[0x22] 39076 1 T5 1 T8 327 T38 1
valid_sources[0x23] 37178 1 T11 1 T12 3 T7 15
valid_sources[0x24] 38116 1 T12 6 T7 11 T8 294
valid_sources[0x25] 38133 1 T11 1 T12 3 T7 4
valid_sources[0x26] 37451 1 T5 1 T106 1 T8 324
valid_sources[0x27] 37869 1 T12 15 T7 1 T199 1
valid_sources[0x28] 37784 1 T106 1 T199 1 T8 316
valid_sources[0x29] 39162 1 T11 1 T12 2 T8 301
valid_sources[0x2a] 36957 1 T5 2 T12 3 T7 21
valid_sources[0x2b] 37081 1 T5 1 T12 5 T7 13
valid_sources[0x2c] 36387 1 T5 1 T11 1 T8 271
valid_sources[0x2d] 38530 1 T5 1 T12 5 T107 1
valid_sources[0x2e] 38133 1 T11 1 T7 35 T106 3
valid_sources[0x2f] 38101 1 T7 8 T199 1 T8 311
valid_sources[0x30] 37974 1 T8 336 T91 4 T9 159
valid_sources[0x31] 37771 1 T11 1 T12 27 T7 2
valid_sources[0x32] 37466 1 T2 1 T8 302 T9 192
valid_sources[0x33] 37601 1 T11 1 T12 4 T106 1
valid_sources[0x34] 39521 1 T12 1 T104 7 T108 1
valid_sources[0x35] 38517 1 T5 1 T12 2 T7 1
valid_sources[0x36] 37528 1 T12 17 T7 4 T100 3
valid_sources[0x37] 38882 1 T12 1 T7 17 T100 1
valid_sources[0x38] 38374 1 T11 1 T7 1 T8 315
valid_sources[0x39] 36869 1 T11 2 T12 1 T8 267
valid_sources[0x3a] 38269 1 T106 5 T199 3 T8 273
valid_sources[0x3b] 38272 1 T5 1 T7 2 T199 1
valid_sources[0x3c] 38426 1 T2 1 T12 22 T100 1
valid_sources[0x3d] 37362 1 T11 1 T12 4 T8 337
valid_sources[0x3e] 37879 1 T12 2 T199 1 T8 303
valid_sources[0x3f] 37475 1 T5 2 T7 36 T199 1
valid_sources[0x40] 37110 1 T11 1 T12 8 T7 3
valid_sources[0x41] 38102 1 T5 2 T11 1 T12 2
valid_sources[0x42] 36864 1 T5 1 T8 304 T38 1
valid_sources[0x43] 37134 1 T7 21 T106 4 T199 1
valid_sources[0x44] 37698 1 T11 1 T12 2 T7 1
valid_sources[0x45] 37975 1 T11 1 T12 5 T7 16
valid_sources[0x46] 37307 1 T5 1 T11 1 T12 1
valid_sources[0x47] 37654 1 T5 1 T11 1 T12 12
valid_sources[0x48] 37411 1 T2 2 T12 4 T7 10
valid_sources[0x49] 37785 1 T7 43 T100 1 T106 3
valid_sources[0x4a] 37877 1 T12 10 T7 18 T106 1
valid_sources[0x4b] 38109 1 T5 1 T12 1 T7 18
valid_sources[0x4c] 36694 1 T7 6 T8 285 T38 2
valid_sources[0x4d] 38228 1 T5 2 T12 2 T7 5
valid_sources[0x4e] 37102 1 T5 4 T12 3 T7 30
valid_sources[0x4f] 38096 1 T11 1 T106 1 T8 311
valid_sources[0x50] 37800 1 T12 1 T7 37 T8 326
valid_sources[0x51] 38249 1 T5 2 T106 3 T108 1
valid_sources[0x52] 37290 1 T5 1 T106 1 T8 328
valid_sources[0x53] 38688 1 T5 3 T12 7 T7 8
valid_sources[0x54] 36529 1 T2 2 T5 1 T12 10
valid_sources[0x55] 37334 1 T5 2 T11 1 T12 7
valid_sources[0x56] 37168 1 T11 1 T12 5 T8 316
valid_sources[0x57] 36680 1 T2 1 T11 1 T12 3
valid_sources[0x58] 38351 1 T5 1 T7 5 T100 1
valid_sources[0x59] 37600 1 T11 1 T12 4 T100 1
valid_sources[0x5a] 37487 1 T5 3 T12 11 T108 1
valid_sources[0x5b] 38887 1 T5 3 T199 1 T8 283
valid_sources[0x5c] 38120 1 T12 13 T199 1 T8 305
valid_sources[0x5d] 37773 1 T11 1 T7 5 T100 2
valid_sources[0x5e] 38080 1 T8 278 T38 1 T91 1
valid_sources[0x5f] 38644 1 T12 5 T7 18 T101 120
valid_sources[0x60] 36867 1 T5 1 T12 13 T7 10
valid_sources[0x61] 38498 1 T1 20 T5 1 T11 1
valid_sources[0x62] 37506 1 T11 1 T12 12 T106 2
valid_sources[0x63] 38183 1 T5 2 T12 14 T7 13
valid_sources[0x64] 36935 1 T5 1 T7 4 T198 4
valid_sources[0x65] 37903 1 T5 2 T12 3 T107 1
valid_sources[0x66] 37978 1 T5 2 T12 7 T106 1
valid_sources[0x67] 38705 1 T5 1 T12 8 T8 282
valid_sources[0x68] 38247 1 T11 1 T12 18 T7 5
valid_sources[0x69] 38303 1 T11 1 T12 12 T199 1
valid_sources[0x6a] 36747 1 T5 1 T12 11 T199 1
valid_sources[0x6b] 38126 1 T12 8 T7 4 T102 1
valid_sources[0x6c] 38295 1 T5 2 T12 12 T106 1
valid_sources[0x6d] 37041 1 T7 26 T199 1 T8 297
valid_sources[0x6e] 38808 1 T12 7 T7 11 T100 1
valid_sources[0x6f] 37969 1 T106 1 T108 1 T8 328
valid_sources[0x70] 37155 1 T5 2 T12 13 T7 1
valid_sources[0x71] 37349 1 T12 7 T8 293 T38 1
valid_sources[0x72] 38482 1 T12 6 T7 40 T106 1
valid_sources[0x73] 38115 1 T12 4 T199 1 T8 339
valid_sources[0x74] 38551 1 T5 1 T11 1 T12 5
valid_sources[0x75] 37373 1 T12 2 T7 5 T100 1
valid_sources[0x76] 38773 1 T5 2 T11 1 T8 316
valid_sources[0x77] 38619 1 T5 1 T12 2 T106 1
valid_sources[0x78] 39046 1 T11 1 T7 6 T107 2
valid_sources[0x79] 37068 1 T12 4 T7 30 T102 1
valid_sources[0x7a] 37578 1 T12 3 T8 302 T9 207
valid_sources[0x7b] 36341 1 T5 1 T199 2 T8 283
valid_sources[0x7c] 37683 1 T5 2 T8 320 T91 1
valid_sources[0x7d] 37648 1 T5 6 T100 1 T102 1
valid_sources[0x7e] 37483 1 T12 9 T7 25 T106 1
valid_sources[0x7f] 37168 1 T5 1 T107 1 T108 1
valid_sources[0x80] 37322 1 T5 2 T12 12 T108 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 2394895 1 T1 10 T2 10 T5 70
values[0x0] all_enables biggest_size 3512776 1 T1 5 T2 7 T5 34
values[0x1] all_enables biggest_size 3511283 1 T1 5 T2 3 T5 36

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